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| 8096c?avr?01/13 features single-package fully-integrated high precision analog frontend 17bit single-ended voltage-adc 7 selectable input channels offset voltage less than 1lsb 18 bit differential current-adc with programmable gain amplifier comparator mode offset voltage less than 5v temperature measurement with ex ternal and internal sensors integrated voltage divider with internal reverse polarity protection for direct sensing of the battery voltage interface lin physical layer according to lin 2.0, 2.1 and saej2602-2 fulfils the oem ?hardware requirements for lin in automotive applications rev. 1.1? lin hardware uart advanced esd and emc performance high-speed mode up to 115kbaud microcontroller high performance, low power avr 8-bit microcontroller 32bit math. extension module (+, ?, x, /) memory 32k/64k in-system self-programmable flash memory 1k eeprom / 4k sram power supply voltage ?27v to +40v extreme low power consumption others package: qfn48, 7x7mm 2 temperature range: ?40c to +125c atmel atmega32hve2/atmega64hve2 8-bit avr microcontroller with precise analog frontend for very accurate volt age and current measurement datasheet
2 atmel ata9999 [datasheet] 8096c?avr?01/13 1. description with the atmega32hve2/atmega64hve2 atmel ? provides an 8-bit avr ? microcontroller with very precise analog frontend for voltage and current measur ement and 32bi t computing power. the circuit is a comp lete single-package system solution for applications like, e.g., 12v lead acid or li-ion battery monitoring or particle filterin g in automotive applications. the device includes 2 dies, the first die (avr mcu) wi th the very precise analog frontend consisting of a 17bit and a 18bit sigma delta adc programmable gain amplifier with various chopper modes and extreme low offset 8-bit microcontroller with 32bit math-extensions module and 32/64kbytes flash memory and a lin (1) system basis chip (lin sbc) including lin transceiver according to the lin2.0, 2.1 and saej2602-2 standards 3.3v low drop voltage regulator window watchdog integrated voltage divider with revers e polarity protection for very precise sensing of the battery voltage the device includes the same lin sb c die as used in the at mel ata6628 lin system ba sis chip from atmel. note: 1. lin: local interconnect network figure 1-1. atmel atmega32hve2/atmega64hve2 block diagram 17-bit adc timer/counter lin sbc avr mcu oscillators temperature reference watchdog voltage regulator lin transceiver supervision and diagnostics low-power avr cpu 32 bit math. extension shunt 12v automotive powernet lin bus +- 18-bit adc mux pga 3 atmel ata9999 [datasheet] 8096c?avr?01/13 2. pin configurations figure 2-1. pinout qfn-48 2.1 pin descriptions 2.1.1 vcc digital supply voltage. 2.1.2 avcc analog supply voltage. 2.1.3 vref internal voltage reference for external decoupling. for details, see section 27. ?band gap reference and temperature sensor? on page 161 . 2.1.4 vrefgnd ground for decoupling of internal voltage reference. do not connect to gnd on pcb. 2.1.5 gnd ground avcc gnd gnd vcc mode tm pvreg vreg vs vbat en ntrig nv1 gnd nv2 pv2 vref vrefgnd pi ni gnd vcc reset 1 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 adc0/pcint0) pa0 adc1/pcint1) pa1 (progen3/sii/exint0/icp1/miso/pcint9) pb7 (progen2/sdi/mosi/pcint8) pb6 (progen1/sdo/sck/pcint7) pb5 (progen0/sio/ss/pcint6) pb4 (t1/txd/pcint5) pb3 (sci/ckout/pcint4) pb2 (rxd/pcint3) pb1 (t0/fh/pcint2) pb0 wd_osc nres txd sp_mode pv1 div_on rxd lin 4 atmel ata9999 [datasheet] 8096c?avr?01/13 2.1.6 port a (pa1..pa0) port a serves as a 2-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). as inputs, port a pin s that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a is connected to the input mux of the voltage adc. to avoid any disturbance fr om port a pins when doing high accuracy vadc measurements, is not recommended to connect noisy digital signals to these pins. port a also serves the functions of various special feat ures of the atmel ? atmega32hve2/atmega64hve2 as listed in section 21.3.1 ?alternate functions of port a? on page 85 . 2.1.7 port b (pb7..0) port b is a 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit) . as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmel atmega32hve2/atmega64hve2 as listed in section 21.3.2 ?alternate functions of port b? on page 86 . 2.1.8 pv2/nv2 filtered positive/negative input from resist or divider connected to vs. used by the voltage adc to measure the battery pack voltage. for details, see section 26. ?adc - analog to digital converter? on page 138 . 2.1.9 pi/ni filtered positive/negative input from exter nal current sense resistor. used by the current adc to measure charge/discharge currents flowing in the batt ery pack. for details, see section 26. ?adc - analog to digital converter? on page 138 . 2.1.10 reset /dw reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in section 31.5 ?external interrupt characteristics? on page 198 . shorter pulses are not guaranteed to generate a reset. this pin is also used as debugwire communication pin. 2.1.11 vs vs represents the power supply to the chip.the lin operating voltage is vs = 5v to 27v. an undervoltage detection is implemented to disable data transmission if vs falls below vs th in order to avoid false bus me ssages. after switching on vs, the ic starts in fail-safe mode, and the voltage regulato r is switched on (i.e., 3. 3v/50ma output capability). the supply current is typically 10a in sleep mode and 40a in silent mode. 2.1.12 vreg the internal 3.3v voltage regulator is capable of driving loads up to 50ma. it is able to supply the microcontroller and other ics on the pcb and is protected against overloads by means of curr ent limitation and over temperature shut-dow n. furthermore, the output voltage is monitored and will cause a reset signal at the nres output pin if it drops below a defined threshold vthun. t o boost up the maximum load current, an external npn transistor ma y be used, with its base connected to the vreg pin and its emitter connected to pvreg. 2.1.13 pvreg the pvreg is the sense input pin of the 3.3v voltage regulator. for normal applications (i.e. when only using the internal outp ut transistor), this pin must be connected to the vreg pin. if an external boosting transistor is used, the pvreg pin must be connected to the output of this trans istor, i.e, its emitter terminal. 5 atmel ata9999 [datasheet] 8096c?avr?01/13 2.1.14 lin a low-side driver with internal current lim itation and thermal shutdown and an internal pull-up resistor compliant with the lin 2.x specification is implemented. the allowe d voltage range is between ?27v and +40v. reverse currents from the lin bus to vs are suppressed, even in the event of gnd sh ifts or battery disconnection. lin receiver thresholds are compatible with the lin protocol specification. the fall time from recessive to dominant bus state and the rise time from dominant to recessive bus sta te are slope controlled. 2.1.15 txd in normal mode the txd pin is the microcontroller interface used to control the state of the li n output. txd must be pulled to ground in order to have a low lin-bus. if txd is high or not conne cted (internal pull-up resistor ), the lin output transistor i s turned off, and the bus is in recessive state. du ring fail-safe mode, this pin is used as output and is signalling the fail-saf e source. it is current-limited to i txdwake ( section 10. ?electrical characteristics lin sbc? on page 25ff ). 2.1.16 rxd this output pin reports the state of the lin- bus to the microcontroller. lin high (recessi ve state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up resistor with typically 5k to pvreg. the ac characteristics can be defined with an external load capacitor of 20pf. the output is short-circuit protected. rxd is switched off in unpowered mode (i.e., vs = 0v). duri ng fail-safe mode it is signalling the fail-safe source. 2.1.17 en the enable input pin controls the operation m ode of the device. if en is high, the ci rcuit is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. t he vreg voltage regulator operat es with 3.3v/5v/50ma output capability. if en is switched to low while txd is still high, the device is forced to silent mode. no data transmission is then possible, a nd the current consumption is reduced to i vs typ. 40a. the vreg regulator has its full functionality. if en is switched to low while txd is low, the device is forc ed to sleep mode. no data transmission is possible, and the voltag e regulator is switched off. 2.1.18 mode with the pin mode you can enable / disable the watchdog of th e lin sbc. connect the mode pin directly or via an external resistor to gnd for normal watchdog operat ion. to debug the software of the connected microcontroller, connect mode pin to pvreg and the watchdog is switched off. note: if you do not use the watchdog from the li n sbc, connect pin mode directly to pvreg. 2.1.19 tm the tm pin is used for final production measurements at atmel ? . in normal application, it has to be always connected to gnd. 2.1.20 nres the reset output pin, an open drain output, switches to low du ring vreg undervoltage or a watchdog failure generated by the lin sbc. 2.1.21 wd_osc the wd_osc output pin provides a typi cal voltage of 1.2v, which supplies an ex ternal resistor with values between 34k and 120k to adjust the watchdog oscillator time. if the watchdog is disabl ed, this voltage is switched of f and you can either tie to gnd or leave this pin open. in the atmega64hve2 operating circuit this pin is left open. 2.1.22 ntrig the ntrig input pin is the trigger input fo r the window watchdog of the lin sbc. a pull- up resistor is implemented. a negative edge triggers the watchdog. the trigger signal (low) must exceed a minimum time t trigmin to generate a watchdog trigger (see also section 9. ?watchdog? on page 23 ). 6 atmel ata9999 [datasheet] 8096c?avr?01/13 2.1.23 div_on the div_on pin is a low voltage input. it is used to switch on or off the internal voltage divider pv1 output directly with no time limitation (see table 2-1 ). it is switched on if div_on is high or it is sw itched off if div_on is low. in sleep mode the div_on functionality is disabled and pv1 is off. an internal pull-down resistor is implemented. 2.1.24 vbatt the vbat is a high voltage input pin to supply the internal volt age divider. in an application with battery voltage monitoring, this pin can be connected to v battery via, e.g., a 47 resistor in series and a 10nf capacitor to gnd. 2.1.25 pv1 pv1 is the voltage divider output of the voltage divider between vbat and nv1. the divi der ratio is 1:24. for applications with battery monitoring, this pin is directly connected to the adc of a microcontroller. for buffering the adc input an external capacitor might be needed. this pin guarantees a voltage and temperature stable output of a vbattery ratio. the pv1 output pin is controlled by the div_on input pin. 2.1.26 sp_mode the sp_mode pin is a low-voltage input. high-speed mode of the transceiver can be activated via a high level during normal mode. return to lin 2.x transceiver mode with slope cont rol is possible if you switch the sp_mode pin to low. 2.1.27 nv1 this pin is directly connected to the base of the voltage divi der. for battery voltage sensing this pin nv1 and pin pv1 should be directly connected to the two inputs of an ad-c onverter. nv1 should be additional connected to gnd. 2.1.28 nc not connected pins are internally connected to gnd. table 2-1. table of voltage divider mode of operation input div_on voltage divider output pv1 fail-safe/normal/ high-speed/silent 0 off 1 on sleep 0 off 1 off 7 atmel ata9999 [datasheet] 8096c?avr?01/13 3. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms t a =25c output current i vreg 50ma v s +40 v pulse time 2min t a =25c output current i vreg 50ma v s 27 v vbat (with 47 /10nf) dc voltage transient voltage due to iso7637 3a, 3b (coupling 1nf) ?1 ?150 +40 +100 v v lin, vbat - dc voltage ?27 +40 v logic pins (rxd, txd, en, nres, ntrig, wd_osc, mode, tm, div_on, sp_mode, pv1) ?0.3 vreg + 0.5v v pin nv1 ?0.3 +0.3 v output current nres i nres +2 ma pvreg dc voltage vreg dc voltage ?0.3 ?0.3 +5.5 +6.5 v v logic pins (pa0-pa1, pi, ni, pb0-pb7, pv2, nv2) ?0.5 vcc + 0.5 v reset ?0.5 +13 v vref ?0.5 vcc + 0.5 v vrefgnd connected via internal metal connection to gnd. do not connect external to gnd. ?0.5 +0.5 ma vcc/avcc ?0.3 +4.5 v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, lin to gnd - pin vbat (10nf) to gnd 6 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) mil-std-883 (m3015.7) 3 kv cdm esd stm 5.3.1 750 v mm esd eia/jesd22-a115 esd stm5.2 aec-q100 (002) 200 v esd hbm following stm5.1 with 1.5k 100pf - pin vs, lin, vbat to gnd 6 kv 8 atmel ata9999 [datasheet] 8096c?avr?01/13 junction temperature lin sbc t j ?40 +150 c junction temperature avr mcu t j ?40 +125 c storage temperature t s ?55 +150 c 3. absolute maximum ratings (continued) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit 4. thermal characteristics parameters symbol min. typ. max. unit thermal shutdown of vreg regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c thermal resistance junction to heat slug r thjc 6 k/w thermal resistance junction to ambient (1) r thja 30 k/w note: 1. jedec multi-layer pcb, air flow. 8096c?avr?01/13 features master and slave operation possible supply voltage ?27v to +40v operating voltage v s = 5v to 27v typically 10a supply current during sleep mode typically 40a supply current in silent mode linear low-drop voltage regulator: normal, fail-safe, and silent mode v reg = 3.3v 2% in sleep mode v reg is switched off vreg-undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output nres high-speed mode up to 115kbaud internal 1:24 voltage divider for v battery sensing negative trigger input for watchdog boosting the voltage regulator possibl e with an external npn transistor lin physical layer according to lin 2.0, 2.1 and saej2602-2 wake-up capability via lin-bus bus pin is overtemperature and short-ci rcuit protected versus gnd and battery adjustable watchdog time via external resistor advanced emc and esd performance fulfills the oem ?hardware requirements for lin in automotive applications rev. 1.1? atmel ? ata6628 lin sbc inside atmel lin system basis chip (lin sbc) lin bus transceiver with 3. 3v regulator and watchdog preliminary datasheet 10 atmel ata9999 [datasheet] 8096c?avr?01/13 5. description the atmel ? lin sbc is a fully integrated lin tr ansceiver, which complies with the li n 2.0, 2.1 and saej2602-2 specifications. it has a low-drop voltage regulator for 3. 3v/50ma output and a window wa tchdog. the voltage regulator is able to source 50ma, but the output current can be boosted by using an external npn tr ansistor. this chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for lin-bus systems. atmel lin sbc is designed to handle the low- speed data communication in vehicles, e. g., in convenience electronics. improved slope control at the lin-driver ensures secure data communication up to 20kbaud. sleep mode and silent mode guarantee very low current consumption. figure 5-1. block diagram high speed mode adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer debounce time internal testing unit control unit slew rate control wake-up bus timer mode select undervoltage reset normal/silent/ fail-safe mode 3.3v/50 ma/ 2% rf filter watchdog rxd ntrig nv1 pv1 pvreg pvreg pvreg tm mode en txd sp_mode receiver normal and fail-safe mode lin wd_osc nres pvreg vreg vs div_on vbat 5k gnd control 11 atmel ata9999 [datasheet] 8096c?avr?01/13 6. functional description 6.1 pin functions for pin functions of the lin sbc please refer to section 2.1 ?pin descriptions? on page 3 . 6.2 physical layer compatibility since the lin physical layer is independent fr om higher lin layers (e.g., the lin pr otocol layer), all nodes with a lin physica l layer according to revision 2.x can be mixed with lin physical layer nodes, which, according to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3), are without any restrictions. 6.3 wake-u events from sleep or silent mode lin-bus en pin 6.4 ground shift the ic does not affect the lin-bus in the event of gnd disconnection. it is able to handle a ground shift up to 11.5% of vs. th is is the mandatory system ground pin. 6.5 txd dominant time-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in dominant state. if txd is fo rced to low for longer than t dom > 27ms, the lin-bus driver is switched to recessive state. nevertheless, when switching to sleep mode, th e actual level at the txd pin is relevant. to reactivate the lin bus driver, switch txd to high (> 10s). 12 atmel ata9999 [datasheet] 8096c?avr?01/13 7. modes of operation figure 7-1. modes of operation 7.1 normal mode thi s i s the normal tran s mitting and receiving mode. the voltage reg u lator i s active and can s o u rce u p to 50ma. the u ndervoltage detection i s activated. the watchdog need s a trigger s ignal from ntrig to avoid re s et s at nre s . if nre s i s s witched to low, the ic change s it s s tate to fail- s afe mode. table 7-1. table of modes mode of operation transceiver pin lin v reg pin mode watchdog pin wd_osc unpowered off recessive on gnd on on fail-safe off recessive 3.3v gnd on 1.23v normal/ high- speed on txd depending 3.3v gnd on 1.23v silent off recessive 3.3v gnd off 0v sleep off recessive 0v gnd off 0v unpowered mode (see section 4.6) a: v s > vs thf b: v s < vs thu c: bus wake-up event fail-safe mode vreg: 3.3v/50ma with undervoltage monitoring communication: off watchdog: on silent mode vreg: 3.3v/50ma with undervoltage monitoring communication: off watchdog: off sleep mode vreg: switched off communication: off watchdog: off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d d c b normal mode vreg: 3.3v/50ma with undervoltage detection watchdog: on high level at pin sp_mode: high-speed mode transceiver 115kbaud lin 2.1 transceiver 20kbaud txd time-out timer on go to sleep command d: nres switches to low go to normal command 13 atmel ata9999 [datasheet] 8096c?avr?01/13 7.2 silent mode a falling edge at en when txd is high switches the ic into si lent mode. the txd signal has to be logic high during the mode select window (see figure 7-2 ). the transmission path is disabled in silent mode. it is possible to switch on the voltage divider via pin div_on. the overall supply current from v bat is a combination of the i vssi = 40a plus the vreg regulator output current i vreg . the 3.3v regulator with 2% tolerance can source up to 50ma . the internal slave termination between the lin pin and the vs pin is disabled in silent mode to minimize the current consumpti on in the event that the lin pin is short-circuited to gnd. onl y a weak pull-up current (typically 10a) between the lin pin and the vs pin is present. silent mode can be activated independently from the actual level on the lin. if an undervo ltage condition occurs, nres is switched to low, and the ic changes its state to fail-safe mode. a voltage less than the lin pre_wake detecti on vlinl at the lin pin activates the inte rnal lin receiver and starts the wake-up detection timer. figure 7-2. switch to silent mode delay time silent mode t d _silent = maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vreg nres txd en normal mode silent mode 14 atmel ata9999 [datasheet] 8096c?avr?01/13 a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and the following rising edge at the lin pin (see figure 7-3 ) result in a remote wake-up request, which is only possible if txd is high. the device switches from silent mode to fail-safe mode. the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rx d pin to interrupt the microcontroller (see figure 7-3 ). en high can be used to switch directly to normal mode. figure 7-3. lin wake-up from silent mode watchdog off start watchdog lead time t d watchdog undervoltage detection active silent mode 3.3v/50ma fail safe mode 3.3v/50ma normal mode low fail-safe mode normal mode en high node in silent mode high high nres en vreg voltage regulator rxd lin bus bus wake-up filtering time t bus txd don't care 15 atmel ata9999 [datasheet] 8096c?avr?01/13 7.3 sleep mode a falling edge at en when txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 7-4 ). in order to avoid any influence to the lin-pin during switching into sleep mode it is possible to switch the en up to 3.2s earlier to low than the txd. theref ore, the best an easiest way are two falling edges at txd and en at the same time. the transmission path is disabled in sleep mode. the supply current i vssleep from v bat is typically 10a. the pv1 output and the vreg regulator are switched off. nres and rxd are low. the internal slave termination between the lin pin and vs pin is disabled to minimize the current consumpti on in the event that the lin pin is short-circuited to gnd. onl y a weak pull-up current (typically 10a) between the lin pin and the vs pin is present. sleep mode can be activated independently from the current level on the lin. a voltage less than the lin pre_wake detecti on vlinl at the lin pin activates the inte rnal lin receiver and starts the wake-up detection timer. figure 7-4. switch to sleep mode delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vreg nres txd en sleep mode normal mode mode select window 16 atmel ata9999 [datasheet] 8096c?avr?01/13 a falling edge at the lin pin follo wed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin lin result in a remote wake-up request. the device switches from sleep mode to fail-safe mode.the vreg regulator is activated, and the internal lin slave termination resistor is swit ched on. the remote wake-up request is indicated by a low lev el at the rxd pin to interrupt the microcontroller (see figure 7-5 ). en high can be used to switch directly from sleep/silent to fail-safe mode. if en is still high after vreg ramp up and undervoltage reset time, the ic switches to the normal mode. figure 7-5. lin wake up from sleep mode regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller reset time low or floating floating watchdog nres en vreg voltage regulator rxd lin bus bus wake-up filtering time t bus txd watchdog off start watchdog lead time t d start-up time delay 17 atmel ata9999 [datasheet] 8096c?avr?01/13 7.4 sleep or silent mode: behavior at a floating lin-bus or a short circuited lin to gnd in sleep or in silent mode the device has a very low current consumption even during shortcir cuits or floating conditions on th e bus. a floating bus can arise if the master pull-up resistor is missing, e.g., if it is switched off when the lin- master is in sleep mode or even if the power supply of the master node is switched off. in order to minimize the current consumption i vs in sleep or silent mode during volta ge levels at the lin-pin below the lin pre- wake threshold, the receiver is activa ted only for a specific time tmon. if t mon elapses while the voltage at the bus is lower than pre-wake detection low (v linl ) and higher than the lin dominant le vel, the receiver is switched off again and the circuit changes back to sleep respectively silent mode. the current consumption is then the result of i vssleep or i vssilent plus i linwake . if a dominant state is reached on t he bus no wake-up will occur. even if the voltage rises above the pre-wake detection high (v linh ), the ic will stay in sleep respectively silent mode (see figure 7-6 ). this means the lin-bus must be above the pre-wake detection threshold v linh for a few microseconds before a new lin wake- up is possible. figure 7-6. floating lin-bus during sleep or silent mode i vssleep/silent i vssleep i vsfail + i linwake i vssleep v busdom v linl i vs t mon lin pre-wake lin dominant state lin bus mode of operation int. pull-up resistor rlin wake-up detection phase off (disabled) sleep/silent mode sleep/silent mode 18 atmel ata9999 [datasheet] 8096c?avr?01/13 if the atmel ? lin sbc is in sleep or silent mode and the vo ltage level at the lin-bu s is in dominant state (v lin < v busdom ) for a time period exceeding t mon (during a short circuit at lin, for example), the ic switches back to sleep mode respectively silent mode. the v s current consumption then consists of i vssleep or i vssilent plus i linwake . after a positive edge at pin lin the ic switches directly to fail-safe mode (see figure 7-7 ). figure 7-7. short circuit to gnd on the lin-bus during sleep- or silent mode sleep/silent mode i vssleep/silent i vsfail + i linwake i vssleep/silent v busdom v linl lin pre-wake lin dominant state lin bus i vs mode of operation int. pull-up resistor rlin off (disabled) on (enabled) wake-up detection phase sleep/silent mode fail-safe mode t mon t mon 19 atmel ata9999 [datasheet] 8096c?avr?01/13 7.5 fail-safe mode the device automatically swit ches to fail-safe mode at system power-up. the voltage regulato r is switched on (v reg = 3.3v/2%/50ma) (see figure 8-1 on page 22 ). the nres output switches to low for t res = 4ms and gives a reset to the microcontroller. lin communicatio n is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a power down of v bat (v s 21 atmel ata9999 [datasheet] 8096c?avr?01/13 8. wake-up scenarios from silent or sleep mode 8.1 remote wake-up via dominant bus state a voltage less than the lin pre_wake detection v linl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. a falling edge at the lin pin followed by a dominant bus level v busdom maintained for a ce rtain time period (t bus ) and a rising edge at pin lin result in a remote wake-up request. a remote wake up from silent mo de is possible only if txd is high. the device switches from silent or sleep mode to fail-safe mode. the vreg voltage regu lator is/remains activated and the internal slave termination resistor is switched on. the remote wake-up re quest is indicated by a low leve l at the rxd pin to generate an interrupt for the microcontroller and a strong pull down at txd. 8.2 wake-up source recognition the device can distinguish between different wake-up sources (see table 7-4 on page 19 ). the wake-up source can be read on the txd and rxd pin in fail-safe mode. these flags are immediately reset if the microcontroller sets the en pin to high (see figure 7-3 on page 14 and figure 7-5 on page 16 ) and the ic is in normal mode. 8.3 fail-safe features during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff , and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during li n overtemperature s witch-off, the vreg regulator works independently. during a short-circuit from lin to gnd the ic can be switched into sleep or silent mode and even in this case the current consumption is lower than 45a in sleep mode and lower than 80a in silent mode. if the shor t-circuit disappears, the ic starts with a remote wake-up. sleep or silent mode: during a floating condition on th e bus the ic switches back to sleep mode/silent mode automatically and thereby the current consumption is lower than 45a/80a. the reverse current is < 2a at the lin pin during loss of v bat . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vreg, the out put limits the output current to i vreglim . because of undervoltage, nres switches to low and sends a reset to the microcontroller if nres is con nected to the microcontroller. the ic switches into fail-safe mode. if the chip temperature exceeds the value t vregoff , the vreg output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of the fa il-safe mode, the vreg voltage will switch on again although en is switched off from th e microcontroller. the microcontroller can start with its normal operation. en pin provides a pull-down resistor to force the tr ansceiver into recessive mode if en is disconnected. rxd pin is set floating if v bat is disconnected. txd pin provides a pull-up resistor to force the tr ansceiver into recessive mode if txd is disconnected. if txd is short-circuited to gnd, it is possible to switch to sleep mode via enable. if the wd_osc pin has a short circuit to gnd and the nt rig signal has a period time > 27ms a reset is guaranteed. if the resistor at the wd_osc pin is disconnected and the ntrig signal has a period time < 46ms a reset is guaranteed. if there is no ntrig signal and short circuit at wd_osc t he nres switches to low after 90ms. for an open circuit (no resistor) at wd_osc it switches to low after typ. 390ms. 22 atmel ata9999 [datasheet] 8096c?avr?01/13 8.4 voltage regulator the voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. it is recommended to use an electrolythic capacitor with c > 1.8f and a ceramic capacitor with c = 100nf. the values of these capacitors can be vari ed by the customer, dep ending on the application. the main power dissipation of the ic is created from the vreg output current i vreg , which is needed for the application. figure 8-1. vreg voltage regulator: ramp-up and undervoltage detection for microcontroller programming, it may be necessary to suppl y the vreg output via an external power supply while the v s pin of the system basis chip is disc onnected. this behavio r is no problem for the system basis chip. nres 3.3v t t t vs 3.3v v thun t res_f t reset t vreg 3.8v 12v vreg 23 atmel ata9999 [datasheet] 8096c?avr?01/13 9. watchdog the watchdog anticipates a trigger signal from the microcontro ller at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time t trigmin > 4s. if a triggering signal is not received, a reset signal will be generated at output nres. the timing basis of the watchdog is provided by the in ternal oscillator. its time period, t osc , is adjustable via the external resistor r wd_osc (34k to 120k ). during silent or sleep mode the watchdog is switched off to reduce current consumption. the minimum time for the first watchdog pulse is required after the undervoltage reset at nres disappears. it is defined as lea d time t d . after wake up from sleep or silent mode, the lead time t d starts with the negative edge of the rxd output. 9.1 typical timing sequence with r wd_osc = 51k the trigger signal t wd is adjustable between 20ms and 64ms using the external resistor r wd_osc . for example, with an external resistor of r wd_osc = 51k 1%, the typical parameters of the watchdog are as follows: t osc = 0.405 r wd_osc ? 0.0004 (r wd_osc ) 2 (r wd_osc in k ; t osc in s) t osc = 19.6s due to 51k t d = 7895 19.6s = 155ms t 1 = 1053 19.6s = 20.6ms t 2 = 1105 19.6s = 21.6ms t nres = constant = 4ms after ramping up the battery voltage, the 5v regulator is switched on. the reset output nres stays low for the time t reset (typically 4ms), then it switches to hi gh, and the watchdog waits for the trigger s equence from the microcontroller. the lead t ime, t d , follows the reset and is t d = 155ms. in this time, the first watchdog pulse from the microcontroller is required. if the trigger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 4ms will reset the microcontroller after t d = 155ms. the times t 1 and t 2 have a fixed relationship. a triggering signal from the microcontroller is an ticipated within the time frame of t 2 = 21.6ms. to avoid false tr iggering from glitches, the trigger pulse must be longer than t trig,min > 200ns. this slope serves to restart the wa tchdog sequence. if the triggering signal fails in this open window t 2 , the nres output will be drawn to ground. a triggering signal during the closed window t 1 immediately switches nres to low. figure 9-1. timing sequence with r wd_osc = 51k t nres = 4ms undervoltage reset watchdog reset t reset = 4ms t trig > 4s t 1 = 20.6ms t 2 = 21ms t 2 t 1 t wd t d = 155ms vreg 3.3v ntrig nres 24 atmel ata9999 [datasheet] 8096c?avr?01/13 9.2 worst case calculation with r wd_osc = 51k the internal oscillator has a tolera nce of 20%. this means that t 1 and t 2 can also vary by 20%. t he worst case calculation for the watchdog period t wd is calculated as follows. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.5ms, t 1,max = 1.2 t 1 = 24.8ms t 2,min = 0.8 t 2 = 17.3ms, t 2,max = 1.2 t 2 = 26ms t wdmax = t 1min + t 2min = 16.5ms + 17.3ms = 33.8ms t wdmin = t 1max = 24.8ms t wd = 29.3ms 4.5ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. table 9-1. typical watchdog timings r wd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 13.3 105 14.0 14.7 19.9 4 51 19.61 154.8 20.64 21.67 29.32 4 91 33.54 264.80 35.32 37.06 50.14 4 120 42.84 338.22 45.11 47.34 64.05 4 25 atmel ata9999 [datasheet] 8096c?avr?01/13 10. electrical characteristics lin sbc 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 5 27 v a 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v vs i vssleep 3 10 14 a a sleep mode, v lin = 0v bus shorted to gnd v s < 14v vs i vssleep_short 6 17 30 a a 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vreg vs i vssi 20 35 45 a a bus recessive v s < 14v (t j = 125c) without load at vreg vs i vssi 25 40 50 a a silent mode v s < 14v bus shorted to gnd without load at vreg vs i vssi_short 25 50 80 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vreg vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus recessive v s < 14v v reg load current 50ma vs i vsdom 50 53 ma a 1.6 supply current in fail-safe mode bus recessive, rxd is low v s < 14v without load at vreg vs i vsfail 0.8 1.5 ma a 1.7 vs undervoltage threshold switch to unpowered mode vs v sthu 4.1 4.4 4.7 v a switch to fail-safe mode vs v sthf 4.4 4.7 4.9 v a 1.8 vs undervoltage threshold hysteresis vs v sth_hys 0.3 v a 2 rxd output pin 2.1 low-level output sink current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low-level output voltage i rxd = 1ma rxd v rxdl 0.4 v a 2.3 internal resistor to pvreg rxd r rxd 3 5 7 k a *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 26 atmel ata9999 [datasheet] 8096c?avr?01/13 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v reg + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high-level leakage current v txd =v reg txd i txd ?3 +3 a a 3.5 low-level output sink current fail-safe mode, wake up v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 2 2.5 8 ma a 4 en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v reg + 0.3v v a 4.3 pull-down resistor v en = v reg en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 ntrig watchdog input pin 5.1 low-level voltage input ntrig v ntrigl ?0.3 +0.8 v a 5.2 high-level voltage input ntrig v ntrigh 2 v reg + 0.3v v a 5.3 pull-up resistor v ntrig = 0v ntrig r ntrig 125 250 400 k a 5.4 high-level leakage current v ntrig = v reg ntrig i ntrig ?3 +3 a a 6 mode input pin 6.1 low-level voltage input mode v model ?0.3 +0.8 v a 6.2 high-level voltage input mode v modeh 2 v reg + 0.3v v a 6.3 high-level leakage current v mode = v reg or v mode = 0v mode i mode ?3 +3 a a 7 lin bus driver 7.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s v a 7.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 7.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 7.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v _losup_1k 0.6 v a 7.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 7.6 pull-up resistor to vs the serial diode is mandatory lin r lin 20 30 47 k a 7.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode =10ma lin v serdiode 0.4 1.0 v d 10. electrical characterist ics lin sbc (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 27 atmel ata9999 [datasheet] 8096c?avr?01/13 7.8 lin current limitation v bus = v bat_max lin i bus_lim 70 120 200 ma a 7.9 input leakage current at the receiver including pull- up resistor as specified input leakage current driver off v bus = 0v v bat = 12v lin i bus_pas_dom ?1 ?0.35 ma a 7.10 leakage current lin recessive driver off 8v < v bat < 18v 8v < v bus < 18v v bus v bat lin i bus_pas_rec 10 20 a a 7.11 leakage current at gnd loss, control unit disconnected from ground. loss of local ground must not affect communication in the residual network. gnd device = v s v bat = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 7.12 leakage current at loss of battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v bat disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 7.13 capacitance on pin lin to gnd lin c lin 20 pf d 8 lin bus receiver 8.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 8.2 receiver dominant state v en = v reg lin v busdom 0.4 v s v a 8.3 receiver recessive state v en = v reg lin v busrec 0.6 v s v a 8.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 v s 0.175 v s v a 8.5 pre_wake detection lin high-level input voltage lin v linh v s ? 2v v s + 0.3v v a 8.6 pre_wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 9 internal timers 9.1 dominant time for wake-up via lin-bus v lin = 0v lin t bus 30 90 150 s a 9.2 time delay for mode change from fail-safe into normal mode via en pin v en = v reg en t norm 5 15 20 s a 9.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v en t sleep 5 15 20 s a 9.4 txd dominant time-out timer v txd = 0v txd t dom 27 55 70 ms a 10. electrical characteris tics lin sbc (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 28 atmel ata9999 [datasheet] 8096c?avr?01/13 9.5 time delay for mode change from silent mode into normal mode via en v en = v reg en t s_n 5 15 40 s a 9.6 monitoring time for wake- up over lin-bus lin t mon 6 10 15 ms a lin bus driver ac parameter with different bus loads load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; r rxd =5k ; c rxd = 20pf; load 3 (medium): 6.8nf, 660 characterized on samples; 10.7 and 10.8 specifie s the timing parameters for proper operation of 20kbit/s, 10.9 and 10.10 at 10.4kbit/s 9.7 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 9.8 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 9.9 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 9.10 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 9.11 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 10 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions (c rxd ): 20pf 10.1 propagation delay of receiver ( figure 10-1 on page 31 ) v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 10.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 11 nres open drain output pin 11.1 low-level output voltage v s 5.5v i nres = 1ma nres v nresl 0.14 v a 11.2 low-level output low 10k to 5v v reg = 0v nres v nresll 0.14 v a 11.3 undervoltage reset time v s 5.5v c nres = 20pf nres t reset 2 4 6 ms a 11.4 reset debounce time for falling edge v s 5.5v c nres = 20pf nres t res_f 1.5 10 s a 10. electrical characterist ics lin sbc (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 29 atmel ata9999 [datasheet] 8096c?avr?01/13 11.5 switch off leakage current v nres = 5.5v nres ?3 +3 a a 12 watchdog oscillator 12.1 voltage at wd_osc in normal or fail-safe mode i wd_osc = ?200a v vs 4v wd_osc v wd_osc 1.13 1.23 1.33 v a 12.2 possible values of resistor resistor 1% wd_osc r osc 34 120 k a 12.3 oscillator period r osc = 34k t osc 10.65 13.3 15.97 s a 12.4 oscillator period r osc = 51k t osc 15.68 19.6 23.52 s a 12.5 oscillator period r osc = 91k t osc 26.83 33.5 40.24 s a 12.6 oscillator period r osc = 120k t osc 34.2 42.8 51.4 s a 13 watchdog timing relative to t osc 13.1 watchdog lead time after reset t d 7895 cycles a 13.2 watchdog closed window t 1 1053 cycles a 13.3 watchdog open window t 2 1105 cycles a 13.4 watchdog reset time nres nres t nres 3.2 4 4.8 ms a 14 vreg voltage regulator in normal/fail-safe and silent mode, vreg and pvreg short-circuited 14.1 output voltage vreg 4v < v s < 18v (0ma to 50ma) vreg vreg nor 3.234 3.366 v a 14.2 output voltage vreg at low vs 3v < v s < 4v vreg vreg low v s ? v d 3.366 v a 14.3 regulator drop voltage v s > 3v, i vreg = ?15ma vs, vreg v d 200 mv a 14.4 regulator drop voltage v s > 3v, i vreg = ?50ma vs, vreg v d 500 700 mv a 14.5 line regulation 4v < v s < 18v vreg vreg line 0.1 0.2 % a 14.6 load regulation 5ma < i vreg < 50ma vreg vreg load 0.1 0.5 % a 14.7 power supply ripple rejection 10hz to 100khz c vreg = 10f v s = 14v, i vreg = ?15ma vreg 50 db d 14.8 output current limitation v s > 4v vreg i vreglim ?240 ?160 ?85 ma a 14.9 load capacity 0.2 < esr < 5 at 100khz vreg c load 1.8 10 f d 14.10 vreg undervoltage threshold referred to vreg v s > 4v vreg v thunn 2.8 3.2 v a 14.11 hysteresis of undervoltage threshold referred to vreg v s > 4v vreg vhys thun 150 mv a 14.12 ramp-up time v s > 4v to v reg = 3.3v c vreg = 2.2f i load = ?5ma at vreg vreg t vreg 320 500 s a 15 div_on input pin 15.1 low-level voltage input div_on v div_on ?0.3 +0.8 v a 15.2 high-level voltage input div_on v div_on 2 v reg + 0.3 v a 15.3 pull-down resistor v div_on = v reg div_on r div_on 125 250 400 k a 15.4 low-level input current v div_on = 0v div_on i div_on ?3 +3 a a 10. electrical characteris tics lin sbc (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 30 atmel ata9999 [datasheet] 8096c?avr?01/13 16 sp_mode input pin 16.1 low-level voltage input sp_mode v sp_mode ?0.3 +0.8 v a 16.2 high-level voltage input sp_mode v sp_mode 2 v reg + 0.3 v a 16.3 pull-down resistor v sp_mode = v reg sp_mode r sp_mode 50 125 200 k a 16.4 low-level input current v sp_mode = 0v sp_mode i sp_mode ?3 +3 a a 17 lin driver in high-speed mode (vsp_mode = vreg) 17.1 transmission baud rate v s = 7v to 18v r lin = 500 , c lin = 600pf lin sp 115 kbaud c 17.2 slope time lin falling edge v s = 7v to 18v lin t sl_fall 1 2 s a 17.3 slope time lin rising edge, depending on rc-load v s = 14v r lin = 500 , c lin = 600pf lin t sl_rise 2 3 s a 18 voltage divider 18.1 divider ratio vbat 5v to 40v pv1 1:24 d 18.2 divider ratio error vs = 5v to 27v pv1 ?2 +2 % a 18.3 divider temperature drift pv1 2 ppm/c c 18.4 vbat range of divider linearity vbat 5 27 v c 18.5 vbat input current vbat = 14v vbat 100 220 a a 18.6 maximum output voltage at pv1 pv1 3 3.1 3.5 v a 18.7 pin capacitance pv1 2 pf d 10. electrical characterist ics lin sbc (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specifie d. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type mean s : a = 100% te s ted, b = 100% correlation te s ted, c = characterized on s ample s , d = de s ign parameter 31 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 10-1. definition of bus timing characteristics txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit 8096c?avr?01/13 features high performance, low power avr ? 8-bit microcontroller advanced risc architecture 124 powerful instructions - most single clock cycle execution additional math extension instruction set 32 x 8 general purpose working registers fully static operation up to 15mips throughput at 15mhz high endurance non-volatile memory segments 32k/64kbytes of in-system self-p rogrammable flash program memory 1kbyte eeprom 4kbytes internal sram write/erase cycles:10, 000 flash/ 100,000 eeprom data retention: 20 years at 85c/100 years at 25c (1) optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation programming lock for software security peripheral features two configurable 8 or 16-bit timers with separate prescaler, optional input capture (ic), compare mode and ctc lin uart serial communication interface with flexible baud-rate generator master/slave spi serial interface 17-bit 8ks/s single-ended voltage-adc wit h 7 selectable input channels and diagnosis modes 18-bit 8ks/s differential current-adc wi th programmable gain, comparator mode and diagnosis modes wake-up timer programmable watchdog timer with separate on-chip oscillator special microcontroller features debugwire on-chip debug system in-system programmable via spi ports power-on reset external and internal interrupt sources sleep modes: idle, power-save and power-down atmel avr microcontroller unit (avr mcu) 8-bit avr microcontroller with 32k/64k bytes in-system programmable flash preliminary datasheet 33 atmel ata9999 [datasheet] 8096c?avr?01/13 11. overview the atmel ? avr mcu is a monitoring circuit, e.g., for sensor or car battery applications with focus on high accuracy and low cost. the device contains two high accuracy adcs and a pr ecision analog voltage and temperature reference, e.g., measurement of battery cell voltage, current and temperature. t he device also contains accurate rc oscillators and a pll, minimizing the external component count. the device contains a dedicated lin/uart macro module, for data input/output using the lin protocol. this interface also supports higher da ta rates than specified in th e lin specification.the device implements low power modes of operation, allowing continuous current monitoring with low current consumption. the feature set makes the atmel avr mcu highly suitab le in, e.g., car batt ery monitoring systems focusing on high performance and low cost. figure 11-1. block diagram the mcu provides the following features: 32k/64k bytes of in-system programmable fl ash with read-while-write capabilities, 1k bytes eeprom, 4kbytes sram, 32 general purpose working register s, 10 general purpose i/o lines, two flexible timer/counters with input capt ure and compare modes, one programmable lin/ua rt, two high accuracy delta sigma adcs for voltage, current and temperature meas urements, a programmable watchdog time r with internal oscillator, debugwire for on-chip debugging, an spi serial port also used for programming, internal and external interrupts and three software selectable power saving modes. the two delta sigma adcs allow simult aneous measurement of battery voltage and current with very high accuracy, temperature measurements using the internal te mperature reference, and contin uous monitoring of the battery current with very low current consumpt ion using the power-save sleep mode. oscill a tor circuits/ clock gener a tion power supervision por a nd reset w a tchdog oscill a tor oscill a tor s a mpling interf a ce w a tchdog timer progr a m logic volt a ge reference volt a ge adc fl a sh spi lin/uart portb (8) pb7 to 0 pa1 to 0 porta (2) data bus avr cpu sram 8/16-bit t/c0 8/16-bit t/c1 v ctat avcc_div nv2 pi ni pv2 vref vrefgnd eeprom w a ke-up timer debugwire vcc reset/dw gnd current adc 34 atmel ata9999 [datasheet] 8096c?avr?01/13 the avr core combines a rich instruction set with 32 general purpose workin g registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is mo re code efficient while achieving throughputs up to ten times fast er than conventional cisc microcontrollers. the device is manufactured using atmel?s high density non-vo latile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system, through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot program running on the avr co re. the boot program can use any interface to download the application program in the application fl ash memory. software in the boot flash section will continue to run while the application flash section is updated, prov iding true read-while-write operation. by combining an 8-bit risc cpu with in- system self-programmable flash and highly accura te analog front-end in a monolithic chip, the atmel ? avr mcu is a powerful microcontroller that provides a highly flexible and cost effective solution. the atmel avr mcu avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/s imulators, and on-chip debugger. 12. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handlin g in c is compiler dependent. please confirm with the c compil er documentation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis? , ?sbic?, ?cbi?, and ?sbi? instru ctions must be replaced with instructions that allow access to exte nded i/o. typically ?lds? and ?sts? combin ed with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 35 atmel ata9999 [datasheet] 8096c?avr?01/13 13. avr cpu core 13.1 overview this section discusses the avr core architecture in general. th e main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memo ries, perform calculations, control peripherals, and handle interrupts. figure 13-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are ex ecuted with a single level pipelining. while one instruction is being executed, the next instruction is pr e-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file co ntains 32 x 8-bit general purpose working regist ers with a single clock cycle access time. this allows single-cycle arithmetic logic unit (a lu) operation. in a typical alu op eration, two operands are output from the registe r file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of thes e address pointers can also be used as an a ddress pointer for look up tables in flas h program memory. these added function registers are the 16-bi t x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic opera tions between registers or between a cons tant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect informatio n about the result of the operation. st a tus a nd control interrupt unit 32 x 8 gener a l purpose registers alu d a t a bus 8-bit d a t a sram w a tchdog timer instruction register instruction decoder eeprom i/o lines i/o module n control lines direct addressing indirect addressing i/o module 2 progr a m counter fl a sh progr a m memory i/o module 1 36 atmel ata9999 [datasheet] 8096c?avr?01/13 program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole addres s space. most avr instructions have a single 16-bit word forma t. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectivel y allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset r outine (before subroutines or in terrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. th e data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its contro l registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate inte rrupt vector in the interrupt vector tabl e. the interrupts have priority in accord ance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space lo cations following those of the register file, 0x20 - 0x5f. in addition, the atmel ? avr mcu has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 13.2 alu ? arithmetic logic unit the high-performance avr alu operates in direct connection wit h all the 32 general purpose workin g registers. within a single clock cycle, arithmetic operations betw een general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithm etic, logical, and bit-functions. some implementations of the architecture also provide a powerful mu ltiplier supporting both signe d/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 13.3 status register the status register contains information about the result of the most recently executed arithmet ic instruction. this informatio n can be used for altering program flow in order to perform condi tional operations. note that the status register is updated afte r all alu operations, as specified in the instruction set refer ence. this will in many cases remove the need for using the dedicated compare instructions, resultin g in faster and more compact code. the status register is not aut omatically stored when enteri ng an interrupt routine and restored when returning from an interrupt. this must be handled by software. 13.3.1 sreg ? avr status register bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interr upt enable register is cleared , none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruct ion to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the inst ruction set reference. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmet ic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 37 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative fl ag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s comple ment arithmetics. see the ?i nstruction set description? for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative re sult in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operat ion. see the ?instruction set description? for detailed information. 13.4 general purpose register file the register file is optimized for the avr enhanced risc in struction set. in order to achieve the required performance and flexibility, the following inpu t/output schemes are supporte d by the register file: one 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input one 16-bit output operand and one 16-bit result input figure 13-2 shows the structure of the 32 general purpose working registers in the cpu. figure 13-2. avr cpu general purpose working registers most of the instructions operating on the regist er file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 13-2 , each register is also assigned a data memo ry address, mapping them directly into the first 32 locations of the user data space. although not be ing physically implemented as sram locations, this memory organization provides great flexibility in access of the register s, as the x-, y- and z-pointer registers can be set to index a ny register in the file. 7 0 addr r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 38 atmel ata9999 [datasheet] 8096c?avr?01/13 13.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their gener al purpose usage. these regist ers are 16-bit address pointers for indirect addressing of the data spac e. the three indirect address registers x, y, and z are defined as described in figure 13- 3 on page 38 . figure 13-3. the x-, y-, and z-registers in the different addressing modes these address registers hav e functions as fixed displacement, automatic increment, and automatic decrement (see the instru ction set reference for details). 13.5 stack pointer the stack is mainly used for storing tem porary data, for storing local variables and for storing return addresses after interru pts and subroutine calls. the stack pointer register always points to the top of the stack. note t hat the stack is implemented as growing from higher memory locations to lower memory locati ons. this implies that a stack push command decreases the stack pointer. the stack pointer points to th e data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by th e program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x100. the stack poin ter is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return addre ss is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with th e pop instruction, and it is incremented by two when data is popped from the stack with return from subroutin e ret or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data sp ace in some implementations of the avr ar chitecture is so small that only spl is needed. in this case, the sph register will not be present. 13.5.1 sph and spl ? stack pointer high and stack pointer low 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 39 atmel ata9999 [datasheet] 8096c?avr?01/13 13.6 instruction execution timing this section describes the general access timing concepts for in struction execution. the avr cp u is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 13-4 shows the parallel instruction fetches and instruction exec utions enabled by the harvard architecture and the fast- access register file concept. this is the basic pipelining concept to obtain up to 1mips per mhz with the corresponding unique results for functions per co st, functions per clocks, an d functions per power-unit. figure 13-4. the parallel instruction fetches and instruction executions figure 13-5 shows the internal timing co ncept for the register file. in a single clock cycle an al u operation usin g two register operands is executed, and the result is stored back to the de stination register. figure 13-5. single cycle alu operation 13.7 reset and interrupt handling the avr provides several different interrupt sources. these in terrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by defaul t defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 70 . the list also determines the priority leve ls of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority. when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user software can w rite logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. th e i-bit is automatically set when a return from inte rrupt instruction ? re ti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these in terrupts, the program counter is vectored to the actu al interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. in terrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be s et and remembered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions o ccur while the global interrupt enable bit is cleared, the corres ponding interrupt flag(s) will be set and remembered until the glob al interrupt enable bit is set, and will t hen be executed by order of priority. clk cpu 1st instruction fetch 1st instruction execute 2nd instruction fetch t1 t2 t3 t4 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch clk cpu t1 register oper a nds fetch result write b a ck alu oper a tion execute to t a l execution time t2 t3 t4 40 atmel ata9999 [datasheet] 8096c?avr?01/13 the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily h ave interrupt flags. if the interrupt condition disappears before t he interrupt is enabled, the interrupt will not be triggered. when the avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status register is not automatically stored when entering an interrupt r outine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the inte rrupts will be immediately disabled. no interrupt will be execute d after the cli instruction, even if it occu rs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. when using the sei instruction to enable in terrupts, the instruction following sei will be executed before any pending interrup ts, as shown in this example. 13.7.1 interrupt response time the interrupt execution response for all the enabled avr interrupts is fo ur clock cycles minimum. af ter four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stac k. the vector is normally a jump to the interrupt rout ine, and this jump takes three clock cycle s. if an interrupt occurs during exec ution of a multi-cycle instruction, this instruction is complete d before the interrupt is ser ved. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routi ne takes four clock cycles. during these fo ur clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 42 atmel ata9999 [datasheet] 8096c?avr?01/13 when using register indirect addressing modes with automatic pr e-decrement and post-increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o registers, and the 4k bytes of internal data sram in the atmel avr mcu are all accessible through all these addressing modes. the register file is described in section 13.4 ?general purpose register file? on page 37 . sram data will be unaffected by all other resets than power-on reset. note however that if a reset occurs while writing data types larger than 8-bit to the sram, the write might only be part ially completed. this can leave, e.g., one byte updated in sra m while the rest of the data word (int, long etc) was not written since the reset canceled the ongoing write operation. figure 14-2. data memory map 14.3.1 data memory access times this section describes the general access timing concepts for internal memory acce ss. the internal data sram access is performed in two clk cpu cycles as described in figure 14-3 . figure 14-3. on-chip data sram access cycles data memory 32 registers 0x000 - 0x001f 64 i/o registers 0x0020 - 0x005f 160 ext. i/o regisrers 0x0060 - 0x00ff internal sram (4k x 8) 0x0100 0x10ff clk cpu t1 d a t a d a t a rd wr address v a lid compute address next instruction write re a d memory access instruction address t2 t3 43 atmel ata9999 [datasheet] 8096c?avr?01/13 14.4 eeprom data memory the atmel ? avr mcu contains 1kbytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the fo llowing, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of eeprom programming, see page 183 and page 186 respectively. 14.4.1 eeprom read /write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 14-1 on page 45 . a self-timing function, howeve r, lets the user software detect when the next byte can be written. if the user code contains in structions that wr ite the eeprom, some precautions must be taken. in order to prevent unintentional eeprom wr ites, a specific write proced ure must be followed. refer to the description of the eeprom control register for details on this. when the eeprom is read, the cpu is halted for four clock cycl es before the next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. 14.5 i/o memory the i/o space definition of the atmel ? avr mcu is shown in section 32. ?register summary? on page 203 . all atmel avr mcu i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transferring data between the 32 general purpose working regi sters and the i/o space. i/o registers within the address range 0x00 - 0x1f are directly bit- accessible using the sbi and cbi instructions. in these registe rs, the value of single bits can be checked by using the sbis and sbi c instructions. refer to the in struction set section for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addre sses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be s upported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi inst ructions will only operate on the specified bit, and can theref ore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 14.5.1 general purpose i/o registers the atmel avr mcu contains three general purpose i/o registers. these registers can be used for storing any information, and they are particularly useful for storing global variables a nd status flags. general purpose i/o registers within the addres s range 0x00 - 0x1f are directly bit-accessible usi ng the sbi, cbi, sbis, and sbic instructions. see section 14.6.4 ?gpior2 ? general purpose i/o register 2? on page 47 , section 14.6.5 ?gpior1 ? general pu rpose i/o register 1? on page 47 , and section 14.6.6 ?gpior0 ? general pu rpose i/o register 0? on page 47 for details. 44 atmel ata9999 [datasheet] 8096c?avr?01/13 14.6 register description 14.6.1 eearh and eearl? the eeprom address register high and low bits 15:10 ? reserved these bits are reserved bits in the atmel avr mcu and will always read as zero. bits 9:0 ? eear9:0: eeprom address the eeprom address registers ? eear specify the eeprom address in the 1k bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 1023. the in itial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 14.6.2 eedr ? the eeprom data register bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read operation, the eedr contains the data read out from the eeprom at the address given by eear. 14.6.3 eecr ? the eeprom control register bits 7:6 ? reserved these bits are reserved bits in the atmel ? avr mcu and will always read as zero. bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines which programming action that will be triggered when writing eepe. it is possible to program data in o ne atomic operation (erase the old value and program the new value) or to split the erase and write operations in two di fferent operations. the programming times for the different modes are shown in table 14-1 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. bit 151413121110 9 8 0x22 (0x42) eear9 eear8 eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl bit 76543210 read/writerrrrrrr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 x x xxxxxxxx bit 76543210 0x20 (0x40) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1f (0x3f) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 45 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 3 ? eerie: eeprom re ady interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready in terrupt generates a constant interrupt when eepe is cleared. bit 2 ? eempe: eeprom master write enable the eempe bit determines whether setting eepe to one causes the eeprom to be written. when eempe is set, set- ting eepe within four clock cycles will wr ite data to the eeprom at the selected address if eempe is zero, setting eepe will have no effect. when eempe has been written to one by soft ware, hardware clears the bit to zero after four clock cycles. see the description of the eepe bit for an eeprom write procedure. bit 1 ? eepe: eeprom write enable the eeprom write enable signal eepe is the write strobe to the eeprom. when address and data are correctly set up, the eepe bit must be written to one to write the val ue into the eeprom. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom write takes place. the following proce dure should be fol- lowed when writing the eeprom (the order of steps 2 and 3 is not essential): 1. wait until eepe becomes zero. 2. write new eeprom address to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical one to the eempe bit while writing a zero to eepe in eecr. 5. within four clock cycles after setting eempe, write a logical one to eepe. caution: an interrupt between step 4 and step 5 will make the wr ite cycle fail, since the eeprom master write enable will time-out. if an interrupt routine a ccessing the eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupted ee prom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eepe bit is clear ed by hardware. the user software can poll this bit and wait for a zero before writing t he next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. caution: a bod reset during eeprom write will inva lidate the result of the ongoing operation. bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logi c one to trigger the eeprom read. the eeprom read access takes one instruction, and the requested data is available i mmediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting t he read operation. if a write operation is in progress, it is neither possi- ble to read the eeprom, nor to change the eear register. the pll is used to time the eeprom accesses and the progra mming time will therefore depend on the pll frequency. table 14-2 lists the typical programming time for eeprom access from the cpu. table 14-1. eeprom mode bits eepm1 eepm0 typ. programming time (1) operation 0 0 9ms erase and write in one operation (atomic operation) 0 1 4.5ms erase only 1 0 4.5ms write only 1 1 ? reserved for future use note: 1. actual timing depends on frequency of the pll. 46 atmel ata9999 [datasheet] 8096c?avr?01/13 the following code examples show one a ssembly and one c fu nction for writing to the eeprom. the examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoing spm command to finish. table 14-2. eeprom programming time symbol number of pll cycles typ programming time, f pll = 14.3 mhz eeprom write (from cpu) 27200 3.4ms assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 49 atmel ata9999 [datasheet] 8096c?avr?01/13 15.1.5 watchdog timer and wake-up timer clock ? clk wdt /clk wut the watchdog timer and wake-up timer are provided with dedicated clock domains. this allows operation in all modes. it also allows very low power operation by utilizing an ul tra low power rc oscillator dedicated to this purpose. 15.2 clock sources the following section describes the clock sources available in the device. the clocks are input to the avr clock generator, and routed to the appropriate modules. the atmel ? avr mcu has 3 on-chip clock sources used to clock the internal logic. table 15-1 shows the clo ck sources and their usage. 15.2.1 pll the pll input clock is the slow rc oscillator. the pll has a fix ed multiplication factor of 112, giving an output clock of 14.3 mhz (typical value). when enabled, the pll will require a settlin g time before it has locked to the target frequency. during th is time, the pll output frequency will be unstable and inaccurate. refer to section 31. ?electrical char acteristics avr mcu? on page 192ff for details on pll and slow rc frequency accuracy. to allow the cpu to start up almost imme diately when the pll is enabled, the pll clock will be divided by two to generate the cpu and i/o clock when the pll is not in lock. when the pll enters lock, the cpu and i/o clock will switch to the full pll frequency. operations that r equire high accuracy of the pll clock should not be started until the pll frequency has reached sufficient accuracy. the pllcsr[lock] bit indicates if the pl l is in lock and could be used as a trigger for high accuracy operations. however, note that even if the pll is locked, some additional ti me may be needed after st art-up before the clock frequency has stabilized within the required tolera nces. this depends on the application requirements. the lock bit in the pll control and st atus register (pllcsr) indicates the lo ck state of the pll. a pll lock change interrupt can be enabled by the pllcie bit. when the cpu wakes up from power-save or power-down, the cpu cl ock source is used to time the start-up, ensuring a valid clock before instruction execution starts. the cpu starts execution before the pl l clock is locked. when waking up from a sleep mode where the pll is disabled, there is an additional de lay of 2 slow rc clock cycles (c krc) before the pll starts up. when the cpu starts from reset, there is an additional delay allowing the supply voltage to reach a stable level before commencing normal operation. the ultra low power rc oscillator is used for timing this real-time part of the start-up time. start-up times are determined by the sut fuses as shown in table 15-2 . table 15-1. clock sources clock source usage pll the clock source for the cpu, i/o and flash. this clock divided by 28 is the default clock source for the adcs. slow rc oscillator the clock source for the pll, and optional clock source for the adcs ultra low power rc oscillator the clock source for the watchdog timer and the wake-up timer. table 15-2. start-up times for the pll sut[1:0] start-up times from power-down and power-save (1) addidtional delay from reset (typical values) 00 (3) 01 2 ckrc + 6 ck 14 ck + 16ms (2) 10 2 ckrc + 6 ck 14 ck + 32ms (2) 11 (4) 2 ckrc + 6 ck 14 ck + 64ms (2) notes: 1. ckrc delay is only added if the pll is disabled when the wake-up event occurs. 2. actual value depends on the frequency of the ulp rc oscillator. the typical values of 16ms, 32ms and 64ms correspond to 2k, 4k and 8k cycles of the ulp rc oscillator, repectively. 3. this setting is reserved for test purpose and should not be used in applications. 4. default setting 50 atmel ata9999 [datasheet] 8096c?avr?01/13 15.2.2 slow rc oscillator the slow rc oscillator provides a 128khz clock (typical value) . the oscillator is factory calibrated, and will operate with no external components. during reset, hardware loads the calibrat ion byte into the sosccal register and thereby automatically calibrates the slow rc oscillator. refer to section 15.6.1 ?sosccala ? slow rc oscillat or calibration register a? on page 51 for details. the slow rc oscilla tor features and automatic temperature compen sation, thus removing the need for run-time calibration or frequency prediction. for details on slow rc frequen cy drift and other characteristics, please refer to refer to section 31. ?electrical characteristics avr mcu? on page 192ff . run-time calibration of the slow rc clock is possible, but this is not recommended due to relatively coarse step size compared to the temperature drift of the frequency. 15.2.3 ultra low power rc oscillator the ultra low power rc oscillator (ulp oscillator) provides a 128khz clock (t ypical value, refer to section 31. ?electrical characteristics avr mcu? on page 192ff ). 15.3 clock output the cpu clock divided by 2 can be output to the clko pin. th e cpu can enable the clock output function by setting the ckoe bit in the mcu control register. the clock will not run in any sleep modes. 15.4 system clock prescaler the atmel ? avr mcu has a system clock prescaler, used to presca le the pll clock. the system clock can be divided by setting the section 15.6.5 ?clkpr ? clock prescale register? on page 52 , and this enables the user to decrease or increase the system clock frequency as the requirement for power cons umption and processing power changes. this system clock will affect the clock frequency of the cp u and all synchronous peripherals. clk i/o , clk cpu and clk flash are divided by a factor as shown in table 15-3 on page 52 . when switching between prescale r settings, the system clock prescaler ensures t hat no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neit her the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the fr equency of the undivided clock, may be faster than the cpu's clock frequency. it is not possible to determi ne the state of the prescale r, and the exact time it takes to switch from one clo ck division to the other cannot be exactly predicted. from the time t he clkps values are written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval , two active clock edges are produced. here, t1 is the previou s clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write th e desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setti ng to make sure the write pr ocedure is not interrupted. 15.5 adc clock prescaler the atmel avr mcu has an adc clock prescaler which is used to prescale the pll clock with a fixed division factor of 28 when this clock is selected as the adc clock source. 51 atmel ata9999 [datasheet] 8096c?avr?01/13 15.6 register description 15.6.1 sosccala ? slow rc osc illator calibration register a bits 7:0 ? scala7:0: slow rc oscillator calibration value a the slow rc oscillator calibration register a is used to trim the slow rc oscillator. the fa ctory-calibrated value is auto- matically written to this register during chip reset, and should not be changed by the sw. the slow rc oscillator calibration register a is protected by a timed sequence. 15.6.2 sosccalb ? slow rc osc illator calibration register b bits 7:0 ? scalb7:0: slow rc oscillator calibration value b the slow rc oscillator calibration register b is used to trim the slow rc oscillator. the fa ctory-calibrated value is auto- matically written to this register during chip reset, and should not be changed by the sw. the slow rc oscillator calibration register b is protected by a timed sequence. 15.6.3 pllcsr ? pll control and status register bits 7:6 ? reserved these bits are reserved and will always read as zero. bit 5 ? swen: pll software enable this bit overrides the normal pll enabling and disabling in power save and power down sleep modes. this bit is imple- mented for test purpose and should never be set by the app lication. when this bit is cleared, the pll operates as described in table 16-2 on page 54 . bit 4 ? lock: pll lock if this bit is logic high, the pll is in lock and the pll outpu t is used as the system clock. otherwise, the pll output is divided by a factor of two to generat e the system clock. bits 3:2 ? reserved these bits are reserved and will always read as zero. bit 1 ? pllcif: pll lock change interrupt flag this flag is set if an edge on the lock signal is detected. the flag is cleared either by writing a logic one to the bit or by executing the corresponding interrupt routine. bit 0 ? lock: pll lock change interrupt enable interrupt enable for the lock change interrupt flag. bit 76543210 (0x66) scala7 scala6 scala5 scala4 scala3 scala2 scala1 scala0 sosccala read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 76543210 (0x67) scalb7 scalb6 scalb5 scalb4 scalb3 scalb2 scalb1 scalb0 sosccalb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 76543210 (0xd8) ? ?swenlock ? ? pllcif pllcie pllcsr read/writer rr/wr r rr/wr/w initial value00000000 52 atmel ata9999 [datasheet] 8096c?avr?01/13 15.6.4 mcucr ? mcu control register bit 5 ? ckoe: clock output when this bit is written to one, the cpu clock divided by 2 is output on the clko pin. 15.6.5 clkpr ? clock prescale register note: 1. see clkps[1:0 ] bit description. bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable chan ge of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. cl kpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewr iting the clkpce bit within this time-out period does neither extend the time-out period, or clear the clkpce bit. bits 6:2 ? reserved these bits are reserved and will always read as zero. bit 1:0 ? clkps[1:0]: clock prescaler select these bits define the divi sion factor between the selected cl ock source and the internal syst em clock. these bits can be written run-time to vary the clock frequency to suit the applic ation requirements. as the divider divides the master clock input to the mcu, the speed of all synchro nous peripherals is reduced when a division factor is used. the division factors are given in table 15-3 . the ckdiv8 fuse determi nes the initial value of the clkps bits. if ckdiv8 is unpr ogrammed, the clkps bits will be reset to ?00?. if ckdiv8 is programmed, cl kps bits are reset to ?11?, giving a division factor of 8 at st art up. this feature should be used if the selected clock source has a higher frequency than the maximum frequ ency of the device at the present operating conditions. note that an y value can be written to the clkps bits regardless of the ckdiv8 fuse set- ting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum fre quency of the device at the present opera ting conditions. the device is shipped with the ckdiv8 fuse programmed. bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? ?ckoe pud ? ? ivsel ivce mcucr read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 65432 1 0 (0x61) clkpce ? ? ? ? ? clkps1 clkps0 clkpr read/writer/w rrrrrr/wr/w initial value0 00000x (1) x (1) table 15-3. system clock prescaler select clkps1 clkps0 clock division factor 0 0 1 0 1 2 1 0 4 1 1 8 53 atmel ata9999 [datasheet] 8096c?avr?01/13 16. power management and sleep modes sleep modes enable the application to shut down unused modul es in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the po wer consumption to the application?s requirements. 16.1 sleep modes figure 15-1 on page 48 presents the di fferent clock systems in the atmel ? avr mcu, and their distribution. the figure is helpful in selecting an appropriate sleep mode. the different sleep modes and their wake up sources is summarized in table 16-1 , and figure 16-1 on page 53 shows a sleep mode state diagram. to enter any of the sleep modes, the se bit in smcr, see section 16.7.1 ?smcr ? sleep mode control register? on page 56 , must be written to logic one and a sleep instruction must be executed. the sm2..0 bits in th e smcr register select which sleep mode will be activated by the sleep instruction. see table 16-3 on page 56 for a summary. if an enabled interrupt o ccurs while the mcu is in a sleep mode, the mcu wa kes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from any sleep mode except power-off. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. figure 16-1. sleep mode state diagram table 16-1. wake-up sources for sleep modes mode wake-up sources wake-up on regular current wut wdt spm/eeprom ready c-adc v-adc other i/o idle x x x x x x x power-save x x x x x power-down x x reset reset from a ll st a tes active reset time-out interrupt interrupt interrupt sleep sleep sleep power-s a ve idle power-down 54 atmel ata9999 [datasheet] 8096c?avr?01/13 16.2 idle mode when the sm1..0 bits are written to 00 , the sleep instruction makes the mcu enter idle mode, stopping the cp u but allowing all peripheral functions to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from exte rnal triggered interrupts as well as internal ones like the timer overflow interrupt. 16.3 power-save mode when the sm1..0 bits are written to 11, the sleep instruction makes the mcu ent er power-save mode. in this mode, the voltage adc, current adc, wake-u p timer (wut) and watchdog timer (wdt) continue operating if enabled. this mode will be the default mode when application software does not require operation of cpu, flash or any of the peripheral units running at the pll clock. if the adcs are configured to operate on the 512khz clock or if the pllscr[swen] bit is set, the pll will be operating. refer to section 26. ?adc - analog to digital converter? on page 138 for details on the adc clock selection. if the current through the sense resistor is so small that the current adc cannot measure it accurately, regular current detection should be enabled to reduce power consumption. the wu t keeps accurately track of t he time so that battery self discharge can be calculated. when waking up from power-save mode, there is a delay fr om the wake-up condition occu rs until the wake-up becomes effective. this allows the clock to restart and become stab le after having been stopped. the wake-up period is defined in section 15.2 ?clock sources? on page 49 . 16.4 power-down mode when the sm1..0 bits are written to 10 , the sleep instruction makes the mcu enter power-down mode. in this mode, the pll and slow rc oscillator (rcosc_slow) are normally stop ped, while the wake-up timer (wut) and watchdog timer (wdt) continue operating if enabled. if the pllcsr[s wen] bit is set, both slowrc oscillator and pll will keep running in this mode. when waking up from power-down mode, there is a delay fr om the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stab le after having been stopped. the wake-up period is defined in section 15.2 ?clock sources? on page 49 table 16-2. active mod u le s in different s leep mode s module mode active idle power-save power-down pll x x x (1)(2) rcosc_ulp x x x x rcosc_slow x x x cpu x flash x 8/16-bit timer x x lin uart x x spi x x v-adc x x x c-adc x x x external interrupts x x x x wut x x x x wdt x x x x notes: 1. depending on adc clock source setting, refer to section 26. ?adc - analog to digital converter? on page 138 for details. 2. if pllcsr[swen] bit is set, pll and slowrc oscillator will always run in power-save mode. 55 atmel ata9999 [datasheet] 8096c?avr?01/13 16.5 power reduction register the power reduction register (prr), see section 16.7.2 ?prr0 ? power redu ction register 0? on page 57 , provides a method to stop the clock to individual peripherals to reduce po wer consumption. the current stat e of the peripheral is frozen and the i/o registers can not be read or written. resources used by the periphera l when stopping the clock will remain occupied, hence the peripheral should in most cases be disabl ed before stopping the clock. waki ng up a module, which is done by clearing the bit in prr, puts the modul e in the same state as before shutdown. module shutdown can be used in idle mode and active mode to significantly reduce t he overall power consumption. in all other sleep modes, the clock is already stopped. 16.6 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operating. all func tions not needed should be disabled. in particular, the following modules may need special consideration when trying to achiev e the lowest possible power consumption. 16.6.1 wake-up timer if the wake-up timer is not needed in the application, the module should be turned off. if the wake-up timer is enabled, it wil l be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes this will contribute significantly to the total current consumption. refer to section 18. ?wake-up timer? on page 68 for details on how to configure the wake-up timer. 16.6.2 watchdog timer if the watchdog timer is not needed in the application, the module sh ould be turned off. if the watchdog timer is enabled, it w ill be enabled in all sleep modes, and hence, always consume power . in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to section 17.3 ?watchdog timer? on page 62 for details on how to configure the watchdog timer. 16.6.3 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to section 21.2.5 ?digital input enable and sleep modes? on page 82 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital in put buffers can be disabled by writing to the digital input di sable register. 16.6.4 on-chip debug system a programmed dwen fuse enables some pa rts of the clock system to be running in all sleep modes. th is will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 16.6.5 voltage adc if enabled, the v-adc will consume power independent of slee p mode. to save power, the v-adc should be disabled by clearing the adcre[vaden] bit when not us ed. when disabling the vadc or making other vadc configuration changes, make sure that the disable command has been synchronized to the adc clock domain before entering sleep mode. adc synchronization is explained in section 26.4.1 ?synchronization of co nfiguration settings? on page 146 . see section 26. ?adc - analog to digital converter? on page 138 for details on v-adc operation. 56 atmel ata9999 [datasheet] 8096c?avr?01/13 16.6.6 current adc if enabled, the c-adc will consume power independent of sleep mode. to save pow er, the c-adc should be disabled by clearing the adcrc[caden] bit wh en not used, or set in regular current detection mode. see section 26. ?adc - analog to digital converter? on page 138 for details on c-adc operation. when disabl ing the cadc or making other cadc configuration changes, make sure that the disable command has been synchro nized to the adc clock domain before entering sleep mode. adc synchronization is explained in section 26.4.1 ?synchronization of configuration settings? on page 146 . 16.6.7 pll if the adcs are configured to operate on the 512khz clock, the pll will be operatin g in power-save mode. to minimize power consumption in the power-save m ode, it is therefore recommended to configur e the adcs to operate on the 128khz clock, allowing the pll to be disabled. also note that the pll will be enabled in all sleep modes if the pllcsr[swen] bit is set. for low power operation it is therefore recommended to cl ear this bit before entering sleep mode.. refer to section 26. ?adc - analog to digital converter? on page 138 for details. 16.6.8 bandgap vo ltage reference the bandgap reference will consume power independent of sleep mode. to save power in the power-down sleep mode, the bandgap reference can be configured in a special sample mode where the v ref voltage is refreshed occasionally. see section 27. ?band gap reference and temperature sensor? on page 161 for details. it is not possible for software to completely disable the bandgap during normal operation. 16.7 register description 16.7.1 smcr ? sleep mode control register the sleep mode control register contai ns control bits for power management. bits 7:3 ? reserved these bits are reserved bits in the atmel ? avr mcu, and will always read as zero. bits 2:1 ? sm1:0: sleep mode select bits 1:0 these bits select between the available sleep modes as shown in table 16-3 . bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the ex ecution of the sleep instruction and to clear it immediately after waking up. bit 76543210 0x33 (0x53) ? ? ? ? ? sm1 sm0 se smcr read/write r r r r r r/w r/w r/w initial value00000000 table 16-3. s leep mode s elect sm1 sm0 sleep mode 0 0 idle 0 1 reserved 1 0 power-down 1 1 power-save 57 atmel ata9999 [datasheet] 8096c?avr?01/13 16.7.2 prr0 ? power reduction register 0 bit 7:4 ? reserved these bits are reserved for future use. for compatibility wit h future devices, these bits must be written to zero when prr0 is written. bit 3 ? prlin: power redu ction lin uart interface writing logic one to this bit shuts down the lin uart inte rface by stopping the clock to the module. when waking up the lin uart again, the lin uart should be re initialized to ensure proper operation. bit 4 ? prspi: power reduction serial peripheral interface writing logic one to this bit shuts down the serial periphe ral interface by stopping the clock to the module. when waking up the spi again, the spi should be rein itialized to ensure proper operation. bit 1 ? prtim1: power re duction timer/counter1 writing a logic one to this bit shuts down the timer/count er1 module. when the timer/counter1 is enabled, operation will continue like before the shutdown. bit 0 ? prtim0: power re duction timer/counter0 writing a logic one to this bit shuts down the timer/count er0 module. when the timer/counter0 is enabled, operation will continue like before the shutdown. bit 7 6 5 4 3 2 1 0 (0x64) ? ? ? ? prlin prspi prtim1 prtim0 prr0 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 58 atmel ata9999 [datasheet] 8096c?avr?01/13 17. system control and reset 17.1 resetting the avr during reset, all i/o registers are set to their initial values , and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the progra m never enables an interrupt source, the interrupt vectors are not used, and regular program c ode can be placed at these locations. the circuit diagram in figure 17-1 on page 59 shows the reset logic. table 19-1 on page 70 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require an y clock source to be running. after all reset sources have gone inactive, a delay counter is in voked, stretching the internal reset. this allows the voltage regulator to reach a stable level before no rmal operation starts. the time-out period of the delay counter is defined by the us er through the sut fuses. the different select ions for the delay period are presented in section 15.2 ?clock sources? on page 49 . 17.2 reset sources the atmel ? avr mcu has five sources of reset: the power-on reset module generates a power-on reset when the voltage regulator starts up. external reset. the mcu is reset when a low level is pr esent on the reset pin for lo nger than the minimum pulse length. watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. brown-out reset. the mcu is reset when v reg is below the brown-out reset threshold, v bot . see section 17.2.4 ?brown-out detection? on page 61 debugwire reset. in on-chip debug mode, the debugwire resets the mcu when giving the reset command. 59 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 17-1. reset logic brown-out detection mcu st a tus register (mcusr) reset circuit debugwire pull-up resistor por s q r data b u s ck sut[1:0] counter reset internal reset timeout spike filter v cc reset /dw del a y counters w a tchdog timer ultr a low power rc oscill a tor clock gener a tor power-on reset circuit ocdrf porf wdrf bodrf extrf v cc 60 atmel ata9999 [datasheet] 8096c?avr?01/13 17.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chi p detection circuit. the detection level is defined in section 31. ?electrical characteristics avr mcu? on page 192ff . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 17-2. mcu start-up, reset tied to v cc figure 17-3. mcu start-up, reset extended externally 17.2.2 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay coun ter starts the mcu after the time-out period ? t tout ? has expired. figure 17-4. external reset during operation v pot v rst v dd reset internal reset time-out t tout v dd reset internal reset time-out v pot v rst t tout t tout reset internal reset time-out v rst 61 atmel ata9999 [datasheet] 8096c?avr?01/13 17.2.3 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 62 for details on operation of the watchdog timer. figure 17-5. watchdog reset during operation 17.2.4 brown-out detection the atmel ? avr mcu has an on-chip brown-out detect ion (bod) circuit for monitoring the v cc level during operation by comparing it to a trigger level v bot = v botideal v ref /1.1. during start-up the vref value will change, see section 27. ?band gap reference and temperature sensor? on page 161 . the trigger level has a hysteresis to ensure spike free brown-out dete ction. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot ? v hyst /2. the bod is enabled by setting the boden fuse in low fuse byte, see section 30.2 ?fuse bits? on page 181 . when the fuse is programmed the bod will be enabled in all modes of operation, e xcept in power-off mode. for applications that do not have an external vcc monitor to generate a reset in case of low vc c, it is recommended to always enable the bod in order to guarantee safe operating conditions for the device. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 17-6 ), the brown-out reset is immediately activated. when v cc increases above th e trigger level (v bot+ in figure 17-6 ), the delay counter starts the mcu after the time-out period t tout has expired. figure 17-6. brown-out reset during operation 1 ck cycle v fet reset internal reset reset time-out wdt time-out t tout v bot- v bot+ t tout v cc reset internal reset time-out 62 atmel ata9999 [datasheet] 8096c?avr?01/13 17.3 watchdog timer 17.3.1 features clocked from separate on-chip oscillator 3 operating modes interrupt system reset interrupt and system reset selectable time-out period from 16ms to 8s optional locking of watchdog configuration after initial configuration programmable hardware fuse watchdog always on (wdton) for fail-safe mode 17.3.2 overview the atmel ? avr mcu has an enhanced watchdog timer (wdt). th e wdt counts cycles of the ultra low power rc oscillator. the wdt gives an interrupt or a system reset when th e counter reaches a given time- out value. in normal operation mode, it is required that the syst em uses the wdr - watchdog timer reset - instru ction to restart the c ounter before the time- out value is reached. if the system doesn't restart the counter, an interrupt or system reset wil l be issued. figure 17-7. watchdog timer in interrupt mode, the wdt gives an interrupt when the timer expi res. this interrupt can be used to wake the device from sleep- modes, and also as a general system timer. one example is to lim it the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang-up in ca se of runaway code. the third mode, interrupt and system reset mode, combines the other two m odes by first giving an interrupt and then switch to system reset mode. this mode will for instance allow a safe shutdow n by saving critical paramet ers before a system reset. the watchdog always on (wdton) fuse, if programmed, will force the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. as a safe-guard against software run-away, changes to th e watchdog configuration can on ly be performed with a timed sequence. the sequence for setting or clearing wde and /or changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watc hdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, writ e the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the watchdog timer. 0.51s 0.13s 16ms 32ms 64ms 0.26s 1.0s 2.0s 4.1s 8.2s w a tchdog presc a ler wdp0 wde watchdog reset wdif wdie wdp1 wdp2 wdp3 mcu reset interrupt ultr a low power rc oscill a tor 63 atmel ata9999 [datasheet] 8096c?avr?01/13 notes: 1. see section 12. ?about code examples? on page 34 2. if the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialization routi ne, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt in r17, sreg ; store sreg value cli ; disable interrupts during timed sequence ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 66 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 5 ? wdp3 : watchdog timer prescaler 3 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different presca- ling values and their corresponding timeout periods are shown in table 17-2 . bit 4 ? wdce: watchd og change enable this bit is used in timed sequences for changing wde and prescaler bits. to clear the wde bit, and/or change the pres- caler bits, wdce must be set. once written to one, har dware will clear wdce after four clock cycles. bit 3 ? wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this means that wd e is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. bits 2:0 ? wdp 2:0: watchdog timer prescaler 2, 1, and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different presca- ling values and their corresponding timeout periods are shown in table 17-2 on page 66 . table 17-1. watchdog timer config u ration wdton (1) wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 1 1 1 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset note: 1. wdton fuse set to ?0? means programmed, ?1? means unprogrammed. table 17-2. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out (1) 0 0 0 0 2kcycles 16ms 0 0 0 1 4kcycles 32ms 0 0 1 0 8kcycles 64ms 0 0 1 1 16kcycles 0.13s 0 1 0 0 32kcycles 0.26s 0 1 0 1 64kcycles 0.51s 0 1 1 0 128kcycles 1.0s 0 1 1 1 256kcycles 2.0s 1 0 0 0 512kcycles 4.1s 1 0 0 1 1024kcycles 8.2s 1 0 1 0 reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 note: 1. the actual timeout value depends on the actual clock period of the ultra low power rc oscillator, refer to sec- tion 15.2.3 ?ultra low power rc oscillator? on page 50 for details. 67 atmel ata9999 [datasheet] 8096c?avr?01/13 17.4.3 wdclr - watchdog timer configuration lock register bits 7:3 ? reserved these bits are reserved and will always read as zero. bits 2:1 ? wdcl[1:0]: watchdog timer configuration lock 1:0 the wdtcsr[6:0] register can be locked from any further software updates afte r initial configuration. once locked, these bits cannot be accessed until the next hardware reset. th is provides a safe method for protecting the register from unintentional modification by software runa way. it is recommended that software configures this register shortly after reset, and then protects the register from further updates. there are two levels fo r register locking to support all opera- tional modes of the watchdog timer. if using the watchdog timer in interrupt mode where wdie must be re-enabled after ea ch timeout, only wdtcsr[5:0] should be locked. when using the watchdog in pure system reset mode, wdtcsr[6:0] should be locked to prevent the watchdog from switching from system reset mode to interrupt mode. to lock wdtcsr[6:0], the following algorithm must be followed: 1. in the same operation, write a logic one to wdcle and wdcl1:0. 2. within the next four clock cycles, in the same operatio n, write a logic zero to wdcle and a logic one to wdcl1. to lock wdtcsr[5:0], the following algorithm must be followed: 1. in the same operation, write a logic one to wdcle and wdcl1:0. 2. within the next four clock cycles, in the same operation, write a logic ze ro to wdcle and w dcl1, and a logic one to wdcl0. bit 0 ? wdcle: watchdog timer configuration lock see ?bits 2:1 ? wdcl[1:0]: watchdog timer configuration lock 1:0? on page 67 for description. bit 76543210 ? ? ? ? ? wdcl1 wdcl0 wdcle wdclr read/writerrrrrr/wr/wr/w initial value00000000 68 atmel ata9999 [datasheet] 8096c?avr?01/13 18. wake-up timer the following section describes the wake-up timer in the atmel ? avr mcu. one wake-up timer interrupt 8 selectable time-out periods separate clock source 18.1 overview the wake-up timer is clocked from the ultra low power rc osc illator. by controlling the wake-up timer prescaler, the wake- up interval can be adjusted from 32 ms to 1 s. figure 18-1. wake-up timer 18.2 register description 18.2.1 wutcsr ? wake-up timer control and status register bit 7 ? wutif: wake-up timer interrupt flag the wutif bit is set (one) when an overflow occurs in the wa ke-up timer. wutif is clear ed by hardware when execut- ing the corresponding interrupt handling vector. alternatively, wutif is cleared by writing a logic one to the flag. when the sreg i-bit, wutie (wake-up timer interrupt enable), an d wutif are set (one), the wake-up timer interrupt is executed. bit 6 ? wutie: wake-up timer interrupt enable when the wutie bit and the i-bit in the status register are set (one), the wake-u p timer interrupt is enabled. the corre- sponding interrupt is executed if a wake-up timer overflow occurs, i.e., when the wutif bit is set. bit 5 ? reserved this bit is reserved and will always read as zero. bit 4 ? wutr: wake-up timer reset when wutr bit is written to one, the wake-up timer is re set, and starts counting from zero. the wutr bit is always read as zero. wutr wutp1 wute wutif clk wut /1k clk wut clk wut /2k clk wut /4k clk wut /8k clk wut /16k clk wut /32k clk wut /64k clk wut /128k w a keup presc a ler 1/4 ultr a low power rc oscill a tor bit 765 4 3210 (0x62) wutif wutie ? wutr wute wutp2 wutp1 wutp0 wutcsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value000 0 0000 69 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 3 ? wute: wake-up timer enable when the wute bit is set (one) the wake-up timer is enabled , and if the wute is cleared (zero) the wake-up timer function is disabled. it is recommended to reset the wa ke-up timer when enabling it, by simultaneously setting the wutr and wute bits. bits 2:0 ? wutp2:0: wake-up timer prescaler 2, 1, and 0 the wutp2:0 bits determine the wake-up timer prescaling when the wake-up timer is enabled. the different prescal- ing values and their corresponding time-out periods are shown in table 18-1 . the wake-up timer sh ould always be reset when changing these bits. table 18-1. wake-up timer prescale select wup2:0 number of ultra low power rc oscillator cycles typical time-out 000 4k(4096) 32ms 001 8k(8192) 64ms 010 16k(16384) 128ms 011 32k(32768) 256ms 100 64k(65536) 512ms 101 128k(131072) 1.0s 110 256k(262144) 2.0s 111 512k(524288) 4.1s 70 atmel ata9999 [datasheet] 8096c?avr?01/13 19. interrupts 19.1 overview this section describes the specifics of the interrupt handling as performed in the atmel ? avr mcu. for a general explanation of the avr interrupt handling, refer to section 13.7 ?reset and interrupt handling? on page 39 . 19.2 interrupt vectors in atmel avr mcu table 19-1. reset and interrupt vectors vector no. program address (1) source interrupt definition 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset, and debugwire reset 2 0x0002 int0 external interrupt 0 3 0x0004 pcint0 pin change interrupt 0 4 0x0006 pcint1 pin change interrupt 1 5 0x0008 wdt watchdog time-out interrupt 6 0x000a wakeup wake-up timer overflow 7 0x000c timer1 ic timer/counter 1 input capture 8 0x000e timer1 compa timer/counter 1 compare match a 9 0x0010 timer1 compb timer/counter 1 compare match b 10 0x0012 timer1 ovf timer/counter 1 overflow 11 0x0014 timer0 ic timer/counter 0 input capture 12 0x0016 timer0 compa timer/counter 0 compare match a 13 0x0018 timer0 compb timer/counter 0 compare match b 14 0x001a timer0 ovf timer/counter 0 overflow 15 0x001c lin status lin status interrupt 16 0x001e lin error lin error interrupt 17 0x0020 spi, stc spi, serial transfer complete 18 0x0022 vadc conv v-adc instantaneous conversion complete 19 0x0024 vadc acc v-adc accumulated conversion complete 20 0x0026 cadc conv c-adc instantaneous conversion complete 21 0x0028 cadc reg cur c-adc regular current 22 0x002a cadc acc c-adc accumulated conversion complete 23 0x002c ee ready eeprom ready 24 0x002e spm spm ready 25 0x0030 pll pll lock change interrupt notes: 1. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the addre ss in this table added to the start address of the boot flash section. 2. when the bootrst fuses are programmed, the device wi ll jump to the boot loader address at reset, see section 29. ?boot loader support ? read-while -write self-programming? on page 167 . 71 atmel ata9999 [datasheet] 8096c?avr?01/13 table 19-2 shows reset and interrupt vectors pl acement for the various combinations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vect ors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the most typical and general program setup for the reset and interrupt vector addresses in atmel avr mcu is: table 19-2. reset and interrupt vectors placement (1) bootrst ivsel reset address interrupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 note: 1. the boot reset addresses for the atmel ? avr mcu are shown in section 29.8.13 on page 176 and section 29.8.14 on page 177 , respectively. for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp int0 ; external interrupt 0 handler 0x0004 jmp pcint0 ; pin change interrupt 0 handler 0x0006 jmp pcint1 ; pin change interrupt 1 handler 0x0008 jmp wdt ; watchdog time-out interrupt 0x000a jmp wake_up ; wake-up timer overflow handler 0x000c jmp tim1_ic ; timer1 input capture handler 0x000e jmp tim1_compa ; timer1 compare a handler 0x0010 jmp tim1_compb ; timer1 compare b handler 0x0012 jmp tim1_ovf ; timer1 overflow handler 0x0014 jmp tim0_ic ; timer0 input capture handler 0x0016 jmp tim0_compa ; timer0 comparea handler 0x0018 jmp tim0_compb ; timer0 compareb handler 0x001a jmp tim0_ovf ; timer0 overflow handler 0x001c jmp lin_status ; lin status handler 0x001e jmp lin_error ; lin error handler 0x0020 jmp spi, stc ; spi, serial transfer complete handler 0x0022 jmp vadc_conv ; v-adc instantaneous conversion complete handler 0x0024 jmp vadc_acc ; v-adc accumulated conversion complete handler 0x0026 jmp cadc conv ; c-adc instantaneous conversion complete handler 0x0028 jmp cadc_rec_cur ; c-adc regular current handler 0x002a jmp cadc_acc ; c-adc accumulated conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp spm_rdy ; store program memory ready handler 0x0030 jmp pll ; pll lock change interrupt handler 0x0031 reset: ldi r16, high(ramend) ; main program start 0x0032 out sph,r16 ; set stack pointer to top of ram 0x0033 ldi r16, low(ramend) 0x0034 out spl,r16 0x0035 sei ; enable interrupts 0x0036 72 atmel ata9999 [datasheet] 8096c?avr?01/13 when the bootrst fuse is unprogrammed, the boot section size set to 2kbytes and the ivsel bit in the mcucr register is set before any interrupts are enabled, the mo st typical and general program setup for the reset and interrupt vector addresses is: address labels code comments 0x0000 reset: ldi r16,high(ramend ; main program start 0x0001 out sph,r16 ; set stack pointer to top ; of ram 0x0002 ldi r16,low(ramend) 0x0003 out spl,r16 0x0004 sei ; enable interrupts 0x0005 73 atmel ata9999 [datasheet] 8096c?avr?01/13 19.3 moving interrupts between application and boot space the general interrupt control re gister controls the placement of the interrupt vector table. 19.4 register description 19.4.1 mcucr ? mcu control register bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are placed at the st art of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of th e boot loader section of the flash. the actual address of the start of the boot flash section is det ermined by the bootsz fuses. refer to section 29. ?boot loader support ? read-while-write self-programming? on page 167 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired value to ivsel while writing a zero to ivce. interrupts will automatically be disabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabled until after the in struction following the write to ivsel. if ivsel is not written, inte rrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is programmed, interrupts are disabled while executing from the application section. if in terrupt vectors are placed in the application section and boot lock bit blb12 is programed, inte rrupts are disabled while executing from the boot loader section. refer to section 29. ?boot loader support ? read-w hile-write self-programming? on page 167 for details on boot lock bits. bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is written or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel descrip- tion above. see code example below. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 75 atmel ata9999 [datasheet] 8096c?avr?01/13 20.3 register description 20.3.1 eicra ? external inte rrupt control register a the external interrupt control register a cont ains control bits for interrupt sense control. bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin in t0 if the sreg i-flag and t he corresponding interrupt mask are set. the level and edges on the external int0 pi n that activate the interrupt are defined in table 20-1 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guar anteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instru ction to generate an interrupt. 20.3.2 eimsk ? external interrupt mask register bits 7:1 ? reserved these bits are reserved and will always read as zero. bit 0 ? int0: external in terrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the external interrupt control register a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int0 pin or level sensed. activity on the pin will cause a n interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. bit 76543210 (0x69) ? ? ? ? ? ? isc01 isc00 eicra read/writerrrrrrr/wr/w initial value00000000 table 20-1. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. bit 76543210 0x1d (0x3d) ? ? ? ? ? ? ? int0 eimsk read/writerrrrrrrr/w initial value00000000 76 atmel ata9999 [datasheet] 8096c?avr?01/13 20.3.3 eifr ? external interrupt flag register bits 7:1 ? reserved these bits are reserved and will always read as zero. bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an inte rrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cl eared by writing a logical one to it. this flag is always clear ed when int0 is configured as a level interrupt. 20.3.4 pcicr ? pin change interrupt control register bits 7:2 ? reserved these bits are reserved bits ins the avr mcu, and will always read as zero. bit 1 ? pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status re gister (sreg) is set (one), pi n change interrupt 1 is enabled. any change on any enabled pcint9:2 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint9 :2 pins are enabled individually by the pcmsk1 register. bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status re gister (sreg) is set (one), pi n change interrupt 0 is enabled. any change on any enabled pcint1:0 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint1 :0 pins are enabled individually by the pcmsk0 register. 20.3.5 pcifr ? pin change interrupt flag register bit 7:2 ? reserved these bits are reserved bits ins the atmel ? avr mcu, and will always read as zero. bit 1 ? pcif1: pin change interrupt flag 1 when a logic change on any pcint9:2 pin triggers an inte rrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint1:0 pin triggers an inte rrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bit 76543210 0x1c (0x3c) ? ? ? ? ? ? ? intf0 eifr read/writerrrrrrrr/w initial value00000000 bit 76543210 (0x68) ? ? ? ? ? ? pcie1 pcie0 pcicr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1b (0x3b) ? ? ? ? ? ? pcif1 pcif0 pcifr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 77 atmel ata9999 [datasheet] 8096c?avr?01/13 20.3.6 pcmsk1 ? pin change mask register 1 bit 7:0 ? pcint9:2: pin change enable mask 9:2 these bits select whether pin change inte rrupt is enabled on the corresponding i/o pi n. if pcint9:2 is set and the pcie1 bit in pcicr is set, pin change interrupt is enabled on the co rresponding i/o pin. if pcint9:2 is cleared, pin change inter- rupt on the corresponding i/o pin is disabled. 20.3.7 pcmsk0 ? pin change mask register 0 bits 7:2 ? reserved these bits are reserved bits ins the atme l avr mcu, and will always read as zero. bit 1:0 ? pcint1:0: pin change enable mask 1:0 each pcint1:0 bit selects whether pin change interrupt is ena bled on the corresponding i/o pin. if pcint1:0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabl ed on the corresponding i/o pin. if pcint1:0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6c) pcint9 pcint8 pcint7 pcint6 pcin t5 pcint4 pcint3 pcint2 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6b) ? ? ? ? ? ? pcint1 pcint0 pcmsk0 read/writerrrrrrr/wr/w initial value 0 0 0 0 0 0 0 0 78 atmel ata9999 [datasheet] 8096c?avr?01/13 21. i/o-ports 21.1 overview all avr ports have true read-modify-write f unctionality when used as general digital i/o ports. this means that the direction o f one port pin can be changed without unintentionally changing the direction of any other pin wit h the sbi and cbi instructions. the same applies when changing drive value (if configured as outpu t) or enabling/disabling of pu ll-up resistors (if configured as input). all port pins have individually selectable pull-up resistor s with a supply-voltage invariant resistance. all i/o pins h ave protection diodes to both v cc and ground as indicated in figure 21-1 . refer to section 31. ?electrica l characteristics avr mcu? on page 192ff for a complete list of parameters. figure 21-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the numbering letter for the port, and a lower case ?n? represents the bit number. howeve r, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in section 21.4 ?register description? on page 88 . three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pi nx. the port input pins i/o location is r ead only, while the data register and the data direction register are read/ write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-u p disable ? pud bit in mcucr disables the pull-up function for a ll pins in all ports when set. using the i/o port as general digital i/o is described in section 21.2 ?ports as general digital i/o? on page 79 . many port pins are multiplexed with alternate functions for the peripheral feat ures on the device. how each alte rnate function interferes with the port pin is described in section 21.3 ?alternate port functions? on page 83 . refer to the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pi ns does not affect the use of t he other pins in the port as gen eral digital i/o. c pin r pu pxn logic see figure ?gener a l digit a l i/o? for det a ils 79 atmel ata9999 [datasheet] 8096c?avr?01/13 21.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 21-2 shows a functional description of one i/o-port pin, here generically called pxn. figure 21-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. d 0 1 q wrx rrx wpx pxn clr reset synchronizer data b u s portxn q q l d q q d q pinxn reset rpx wdx: write ddrx wrx: wpx: rpx: rrx: read portx register read portx pin write portx register rdx: write portx read ddrx pud: pullup disable clk i/o : sleep: i/o clock sleep control rdx clk i/o pud wdx sleep d q clr ddxn q 80 atmel ata9999 [datasheet] 8096c?avr?01/13 21.2.1 configuring the pin each port pin consists of three register bi ts: ddxn, portxn, and pinxn. as shown in section 21.4 ?register description? on page 88 , the ddxn bits are accessed at the ddrx i/o address, the po rtxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pi n. if ddxn is written logic one , pxn is configured as an outp ut pin. if ddxn is written logic zero, px n is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pul l-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-state d when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pi n is configured as an output pin, the port pin is driven high (one). if portxn is wri tten logic zero when the pin is configured as an ou tput pin, the port pin is driven low (zero). 21.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 21.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and ou tput high ({ddxn, portxn} = 0b1 1), an intermediate state with either pull-up enabled {ddx n, portxn} = 0b01) or output lo w ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully acceptable, as a hi gh-impedant environment will not notice the difference between a strong high driver a nd a pull-up. if this is not the case, the pud bit in the mcucr re gister can be set to disable all pull-ups in all ports. switching between input with pull- up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({dd xn, portxn} = 0b11) as an intermediate step. table 21-1 summarizes the control signals for the pin value. table 21-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 81 atmel ata9999 [datasheet] 8096c?avr?01/13 21.2.4 reading the pin value independent of the setting of data direct ion bit ddxn, the port pin can be read th rough the pinxn register bit. as shown in figure 21-2 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the in ternal clock, but it also introduces a delay. figure 21-3 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 21-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first fallin g edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched wh en the system clock goes low. it is clocked into the pinxn register at the succeeding posit ive clock edge. a s indicated by the two arrows tpd,max and tp d,min, a single signal transi tion on the pin will be dela yed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 21-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronize r is 1 system clock period. figure 21-4. synchronization when reading a software assigned pin value system clk instructios sync latch pinxn r17 xxx xxx 0x00 0xff in r17, pinx t pd, m a x t pd, min system clk instructios sync latch pinxn r16 r17 out portx, r16 nop 0x00 0xff 0xff in r17, pinx t pd 82 atmel ata9999 [datasheet] 8096c?avr?01/13 the following code example shows how to set port b pins 0 and 1 hi gh, 2 and 3 low, and define the port pins from 4 to 7 as inpu t with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. 21.2.5 digital input enable and sleep modes as shown in figure 21-2 on page 79 , the digital input signal can be clamped to gr ound at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mcu sleep cont roller in power-save mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v reg /2. sleep is overridden for port pins enabled as external interrupt pi ns. if the external interrupt request is not enabled, sleep i s active also for these pins. sleep is also overridden by various other alternate f unctions as described in section 21.3 ?alternate port functions? on page 83 . if a logic high level (?one?) is present on an asynchronous exte rnal interrupt pin configured as ?interrupt on rising edge, fal ling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 21.2.6 unconnected pins if some pins are unused, it is recommended to ensure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described abov e, floating inputs should be avoided to reduce current consumption in all other modes where the digital inpu ts are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. in this case, the pull-up wi ll be disabled during reset. if low power consumption during reset is im portant, it is recommended to use an external pull-up or pull - down. connecting unused pins directly to v cc or gnd is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 84 atmel ata9999 [datasheet] 8096c?avr?01/13 table 21-2 summarizes the function of the overriding signals. the pin and port indexes from figure 21-5 on page 83 are not shown in the succeeding tables. the overriding signals are gene rated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alte rnate function. refer to the alternate func tion description fo r further details. table 21-2. generic description of overri ding signals for al ternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the se tting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the m cu state (normal mode, sleep mode). di digital input this is the digital input to alternate function s. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/f rom alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 85 atmel ata9999 [datasheet] 8096c?avr?01/13 21.3.1 alternate functions of port a the port a pins with alternate functions are shown in table 21-3 . the alternate pin configuration is as follows: adc0/sgnd/pcint0 - port a, bit0 adc0: voltage adc input0. this pin can serve as input 0 for the voltage adc. sgnd: voltage adc sgnd. this pin can serve as signal ground for the voltage adc. pcint0. pin change interrupt 0. this pin can serve as external interrupt source. adc1/sgnd/pcint1 - port a, bit1 adc1: voltage adc input1. this pin can serve as input 1 for the voltage adc. sgnd: voltage adc sgnd. this pin can serve as signal ground for the voltage adc. pcint1: pin change interrupt 1. this pin can serve as external interrupt source. these pins can serve as external interrupt source table 21-4 relates the alternate functions of port a to the overriding sig- nals shown in figure 21-5 on page 83 . table 21-3. port a pins alternate functions port pin alternate function pa1 adc1/sgnd/pcint1 (adc input 1, signal ground or pin change interrupt 1) pa0 adc0/sgnd/pcint0 (adc input 0, signal ground or pin change interrupt 0) table 21-4. overriding signals for alternate functions in pa1:pa0 signal name pa1/adc1/sgnd/pcint1 pa0/adc0/sgnd/pcint0 puoe 0 0 puov 0 0 ddoe vamux = 001 vamux = 010 ddov 1 1 pvoe vamux = 001 vamux = 010 pvov 0 0 ptoe - - dieoe pa1did | (pcint1 pcie0) pa0did | (pcint0 pcie0) dieov pa1did pa0did di pcint1 input pcint0 input aio adc1 input sgnd input adc0 input sgnd input 86 atmel ata9999 [datasheet] 8096c?avr?01/13 21.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 21-5 . the alternate pin configuration is as follows: miso/icp10/int0/pcint 9 - port b, bit7 miso: master data input/slave data output pin for spi channel . when the spi is enabled as a master, this pin is config- ured as an input regardless of the setting of ddb7. when the spi is enabled as a slav e, the data direction of this pin is controlled by ddb7. when the pin is forc ed by the spi to be an input, the pull-up can still be controlled by the portb7 bit. when not operating in spi mode, this pin can serve as an external interrupt source. icp10, timer1 input capture sour ce 0. the pb7 pin can serve as input capture source for timer1. int0, external interrupt source 0: the pb7 pin can serve as an external interrupt source to the mcu. pcint9: pin change interrupt 9. this pin can serve as external interrupt source. mosi/pcint8 - port b, bit6 mosi, spi master data ou tput/slave data input for spi c hannel. when the spi is enabled as a slave, this pin is config- ured as an input regardless of the setting of ddb6. when the spi is enabled as a master, the data direction of this pin is controlled by ddb6. when the pin is forc ed by the spi to be an input, the pull-up can still be controlled by the portb6 bit. when not operating in spi mode, this pin can serve as an external interrupt source. pcint8: pin change interrupt 8. this pin can serve as external interrupt source. sck/pcint7 - port b, bit5 sck, master clock output/slave clock input pin for spi channel. when the spi is en abled as a slave, this pin is config- ured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forc ed by the spi to be an input, the pull-up can still be controlled by the portb5 bit. pcint7: pin change interrupt 7. this pin can serve as external interrupt source. ss /pcint6 - port b, bit4 ss, slave select input: when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb4. as a slave, the spi is activated when this pin is driven low. when the spi is enable d as a master, the data direc- tion of this pin is controlled by ddb4. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb4 bit. when not operating in spi mode, this pi n can serve as clock output, cpu clock divided by 2. see ?clock output? on page 28. pcint6: pin change interrupt 6. this pin can serve as external interrupt source. txd/pcint5 - port b, bit3 txd: this pin can serve as txd pin for the lin interface. pcint5: pin change interrupt 5. this pin can serve as external interrupt source. table 21-5. port b pins alternate functions port pin alternate functions pb7 miso/icp10/int0/pcint9 (spi bus ma ster input/slave output, timer1 input capture source0, external interrupt or pin change interrupt 9) pb6 mosi/pcint8 (spi bus mast er output/slave input or pin change interrupt 8) pb5 sck/pcint7 (spi bus serial clock or pin change interrupt 7) pb4 ss /pcint6 (spi bus slave select input or pin change interrupt 6) pb3 txd/pcint5 (lin txd or pin change interrupt 5) pb2 ckout/pcint4 (clock output or pin change interrupt 4) pb1 rxd/pcint3 (lin rxd or pin change interrupt 3) pb0 fh/pcint2 (force high or pin change interrupt 2) 87 atmel ata9999 [datasheet] 8096c?avr?01/13 ckout/pcint4 - port b, bit2 ckout: clock output. this pin can serve as clock output pin. pcint4: pin change interrupt 4. this pin can serve as external interrupt source. rxd/pcint3 - port b, bit1 rxd: this pin can serve as rxd pin for the lin interface. pcint3: pin change interrupt 3. this pin can serve as external interrupt source. fh/pcint2 - po rt b, bit0 fh: force high. when the pboe0 bit in the pbov register is set, this pin is forced high. pcint2: pin change interrupt 2. this pin can serve as external interrupt source. table 21-6. overriding signals for alternate functions in pb7:pb4 signal name pb7/miso/icp10/ int0/ pcint9 pb6/mosi/pcint8 pb5/sck/pcint7 pb4/ss /pcint6 puoe spe master spe master spe master spe master puov portb7 pud portb7 pud portb7 pud portb7 pud ddoe spe master spe master spe master spe master ddov 0 0 0 0 pvoe spe master spe master spe master 0 pvov spi slave spi master ptoe 0 0 0 0 dieoe pcint9 pcie | int0 enable pcint8 pcie pcint7 pcie pcint6 pcie dieov 1 1 1 1 di int0 icp10 spi master pcint9 spi slave pcint8 sck pcint7 ss pcint6 aio - - - - table 21-7. overriding signals for alternate functions in pb3:pb0 signal name pb3/txd/pcint5 pb2/ckout/ pcint4 pb1/rxd/ pcint3 pb0/fh/pcint2 puoe lintxen ckoe linrxen pboe0 puov lintxd pboe3 portb3 0 portb2 pud 0 ddoe lintxen ckoe linrxen pboe0 ddov lintxd pboe3 ckoe 0 1 pvoe lintxen ckoe 0 pboe0 pvov lintxd pboe3 ckout 0 1 ptoe 0 0 0 0 dieoe pcint5 pcie (pcint4 pcie) | ckoe pcint3 pcint2 pcie dieov 1 pcint4 pcie | ckoe 1 1 di t1 pcint5 linrxd pcint4 pcint3 t0 pcint2 aio - - - - 88 atmel ata9999 [datasheet] 8096c?avr?01/13 21.4 register description 21.4.1 mcucr ? mcu control register bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are con- figured to enable the pull-ups ({ddxn, portxn} = 0b01). see section 21.2.1 ?configuri ng the pin? on page 80 for more details about this feature. 21.4.2 porta ? port a data register 21.4.3 ddra ? port a data direction register 21.4.4 pina ? port a input pins address 21.4.5 portb ? port b data register 21.4.6 ddrb ? port b data direction register bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? ? ckoe pud ? ? ivsel ivce mcucr read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x02 (0x22) ? ? ? ? ? ? porta1 porta0 porta read/writerrrrrrr/wr/w initial value00000000 bit 76543210 0x01 (0x21) ? ? ? ? ? ? dda1 dda0 ddra read/writerrrrrrr/wr/w initial value00000000 bit 76543210 0x00 (0x20) ? ? ? ? ? ? pina1 pina0 pina read/writerrrrrrr/wr/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial val u e 00000000 89 atmel ata9999 [datasheet] 8096c?avr?01/13 21.4.7 pinb ? port b input pins address 21.4.8 pbov ? port b override bit 7 ? pbovce: port b override change enable the pboe0 bit can only be changed by a timed sequence: 1. in the same operation, write one to the pbovce bi t and zero to all other bits in the pbov register. 2. within the next four clock cycles, write zero to the pbovce bit and the desired values to the pboe0 bit. this must be done in one operation. bits 6:4 - reserved these bits are reserved bits and will always read as zero. bit 3 - pboe3: port b override enable 3 this bit overrides normal driving capabilities for the lin transmit signal. if this bit is set, the lin transmit signal may eit her be using the internal pull-up transistor or tristating the por t for the lintx high value, depending on the portb3 setting. in both cases the pin will be driven ac tively low for the lintx low value. when the pboe3 bit is cleared, normal lintx driving capabilities will be restored and the pin will be driven actively high for the lintx high value and and driven actively low for the lintx low value. this is regardless of the portb3 setting. note that when the lin module is disabled, the pboe3 bit has no effect on the port functionality. the lintx driving capabilities is shown in table 21-8 . bits 2:1 - reserved these bits are reserved bits and will always read as zero. bit 0 - pboe0: port b override enable 0 when this bit is set, pb0 is set to one re gardless of settings in the portb, ddrb and pinb registers. when this bit is cleared, pb0 the overriding is disabled. bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 (0xdc) pbovce ? ? ? pboe3 ? ? pboe0 pbov read/write r/w r r r r/w r r r/w initial value00000000 table 21-8. lintx driving capabilities pboe3 portb3 lintx low lintx high 0 x active low active high 1 0 active low tristated 1 1 active low internal pull-up 90 atmel ata9999 [datasheet] 8096c?avr?01/13 22. timer/counter0 and time r/counter1 prescalers 22.1 overview timer/counter1 and timer/counter0 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 22.1.1 internal clock source the timer/counter can be clocked directly by the system clock (by settin g the csn2:0 = 1). this prov ides the fast est operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 22.1.2 prescaler reset the prescaler is free running, i.e., operates independently of t he clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs whe n the timer is enabled and clocked by the pr escaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, o r 1024). it is possible to use the prescaler reset for synchronizing the ti mer/counter to program execution. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a pr escaler reset will affect the prescaler per iod for all timer/counters it is connected to. figure 22-1. prescaler for timer/counter timer/counter n clock source clk tn clk i/o psrsync tn 10-bit t/c presc a ler 0 csn0 ck/8 ck/64 ck/256 ck/1024 csn1 csn2 synchroniz a tion cle a r 91 atmel ata9999 [datasheet] 8096c?avr?01/13 22.2 external clock source an external clock source applied to the tn pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by the pin syn chronization logic. the synch ronized (sampled) signal is then passed through the edge detector. figure 22-2 shows a functional equivalent block diagram of the tn synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock (clk i/o ). the latch is transparen t in the high period of the internal system clock. the edge detector generates one clk tn pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. see table 22-1 on page 92 for details. figure 22-2. tn pin sampling the synchronization an d edge detector logic introduces a delay of 2.5 to 3.5 syst em clock cycles from an edge has been applied to the tn pin to the counter is updated. enabling and disabling of the clock input must be done when tn has been st able for at least one system clock cycle, otherwise it is a risk that a false timer/ counter clock pulse is generated. each half period of the exte rnal clock applied must be lon ger than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the syst em clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequen cy of an external clock it ca n detect is half the sampling frequency (nyquist sampling t heorem). however, due to vari ation of the system clock frequ ency and duty cycle caused by oscillator source (crystal, reso nator, and capacitors) tolerances, it is reco mmended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. note: the synchronization logic on the input pins ( tn) is shown in figure 22-2 . tn synchroniz a tion edge detector tn_sync (to clock select logic) q le d q d q d clk i/o 92 atmel ata9999 [datasheet] 8096c?avr?01/13 22.3 register description 22.3.1 tccrnb ? timer/counte r n control register b bits 2, 1, 0 ? csn2, csn1, csn0: clock select0, bi t 2, 1, and 0 the clock select n bits 2, 1, and 0 define the prescaling source of timer n. if external pin modes are used for the timer/counter n, transi tions on the tn pin will clock the counter even if the pin is configured as an output. th is feature allows software control of the counting. 22.3.2 general timer/counter control register ? gtccr bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchroni zation mode. in this mode, the value that is written to the psrsync bit is kept, hence keeping the corresponding pre scaler reset signals asserted. this ensures that the cor- responding timer/counters are halted and can be configur ed to the same value without the risk of one of them advancing during configuration. when the tsm bit is written to zero the psrsync bit is cleared by hardware, and the timer/counters start counting simultaneously. bit 0 ? psrsync: prescaler reset when this bit is one, timer/counter1 a nd timer/counter0 prescaler will be reset. this bit is normally cleared immedi- ately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 76543210 ? ? ? ? ? csn2 csn1 csn0 tccrnb read/write r r r r r r/w r/w r/w initial value00000000 table 22-1. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped) 0 0 1 clk i/o /(no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654321 0 tsm ? ? ? ? ? ? psrsync gtccr read/writer/wrrrrrrr/w initial value0000000 0 93 atmel ata9999 [datasheet] 8096c?avr?01/13 23. timer/counter(t/c0, t/c1) 23.1 features clear timer on compare match (auto reload) input capture unit four independent interrupt sources (tovn, ocfna, ocfnb, icfn) 8-bit mode with two independent output compare units 16-bit mode with one independent output compare unit 23.2 overview timer/counter n is a general purpose 8-/16-bit timer/counte r module, with two/one output co mpare units and input capture feature. the atmel ? avr mcu has two timer/counters, time r/counter0 and timer/counter 1. the functionality for both timer/counters is described below. timer/counter0 and timer/counter1 ha ve different timer/counter registers, as shown in section 32. ?register summary? on page 203 . the timer/counter general operation is described in 8-/16-bit mode. a simplified block diagram of the 8-/16-bit timer/counter i s shown in figure 23-1 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the section 23.10 ?register description? on page 104 . figure 23-1. 8-/16-bit time r/counter block diagram control logic tcntnl fixed top v a lue tcntnh timer/counter count cle a r direction clk tn ocrna ocrnb == tccrna tccrnb edge detector (from presc a ler) clock select top tovn (int. req.) ocna (int. req.) ocnb (int. req.) icfn (int. req.) tn edge detector noise c a nceler data bus = icpn1 icpn2 icpn0 94 atmel ata9999 [datasheet] 8096c?avr?01/13 23.2.1 registers the timer/counter low byte register (tcntnl) and output compare registers (ocrna and o crnb) are 8-bit registers. interrupt request (abbreviated to int.req. in figure 23-1 on page 93 ) signals are all visible in the timer interrupt flag register (tifr). all interrupts are individually masked with the timer in terrupt mask register (timsk). ti fr and timsk are not shown in the figure. in 16-bit mode the timer/counter consists one more 8-bit register, the timer/counter high byte register (tcntnh). furthermore, there is only one output compare unit in 16- bit mode as the two output compare registers, ocrna and ocrnb, are combined to one 16-bit output compare register. o crna contains the low byte of the word and ocrnb contains the higher byte of the word. when accessing 16-b it registers, special procedures described in section 23.9 ?accessing registers in 16-bit mode? on page 102 must be followed. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block controls which clock source and edge the timer/counte r uses to increment its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referr ed to as the timer clock (clk tn ). 23.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the module number, e.g. , timer/counter number. a lower case ?x? replaces the unit, e. g., ocrnx and icpnx describes ocrna/b and icp1/0x . however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0l for accessing timer/counter0 counter value and so on. the definitions in table 23-1 are also used extensively throughout the document. 23.3 timer/counter clock sources the timer/counter can be clocked internally, via the prescaler, or by an external clock source. the clock select logic is controlled by the clock select (csn2:0) bi ts located in the timer/count er control register n b (t ccrnb), and controls which clock source and edge the timer/counter uses to increment its value. the timer/count er is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk tn ). for details on clock sources and prescaler, see section 22. ?timer/counter0 and timer/counter1 prescalers? on page 90 table 23-1. definitions bottom the counter reaches the bottom when it becomes 0. max the counter reaches its maximum when it beco mes 0xff (decimal 255) in 8-bit mode or 0xffff (decimal 65535) in 16-bit mode. top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff/0xffff (max) or the value stored in the ocrna register. 95 atmel ata9999 [datasheet] 8096c?avr?01/13 23.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 23-2 on page 95 shows a block diagram of the counter and its surroundings. figure 23-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. clk t n timer/counter clock, referred to as clk tn in the following. top signalize that tcntn has reached maximum value. the counter is incremented at each timer clock (clk tn ) until it passes its top value and then restarts from bottom. the counting sequence is determined by the sett ing of the wgmn0 bits located in the ti mer/counter control register (tccrna). for more details about counting sequences, see section 23.8 ?timer/counter timing diagrams? on page 100 . clk tn can be generated from an external or internal clock source, select ed by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcnt n value can be accessed by the cpu, regardless of whether clk tn is present or not. a cpu write overrides (has priority ov er) all counter clear or count operations. the timer/counter overflow flag (tovn) is set when the counter reaches the maxi mum value and it can be used for generating a cpu interrupt. 23.5 modes of operation the mode of operation is defined by the timer/counter widt h (tcwn), input capture enab le (icenn) and the waveform generation mode (wgmn0)bits in section 23.10.1 ?tccrna ? timer/counter n control register a? on page 104 . table 23-2 on page 95 shows the different modes of operation. top tovn (int. req.) data b u s control logic tcntn clk tn count edge detector (from presc a ler) clock select tn table 23-2. modes of operation mode icenn tcwn wgmn0 timer/counter mode of operation top update of ocrx at tov flag set on 0 0 0 0 normal 8-bit mode 0xff immediate max (0xff) 1 0 0 1 8-bit ctc ocrna immediate max (0xff) 2 0 1 0 16-bit mode 0xffff immediate max (0xffff) 3 0 1 1 16-bit ctc ocrnb, ocrna immediate max (0xffff) 4 1 0 0 8-bit input capture mode 0xff ? max (0xff) 5 1 1 0 16-bit input capture mode 0xffff ? max (0xffff) 96 atmel ata9999 [datasheet] 8096c?avr?01/13 23.5.1 normal 8-bit mode in the normal mode, the counter (tcntnl) is incrementing until it overruns when it passes its maximum 8-bit value (max = 0xff) and then restarts from the bottom (0x00), see table 23-2 on page 95 for bit settings. the overflow flag (tovn) will be set in the same timer clock cycle as the tcntnl becomes zero. the tovn flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer over flow interrupt that automatically clears the tovn flag, the time r resolution can be increased by software. there are no special cases to consider in the normal 8-bit mode, a new counter value can be written anytime. the output co mpare unit can be used to generate interrupts at some given time. 23.5.2 clear timer on compare match (ctc) 8-bit mode in clear timer on compare or ctc mode, the ocrna regist er is used to manipulate the counter resolution, see table 23-2 on page 95 for bit settings. in ctc mode the counter is cleared to zero when the counter value (t cntn) matches the ocrna. the ocrna defines the top value for the counter, hence also its reso lution. this mode allows greater control of the compare match output frequency. it also simplifies th e operation of counting external events. the timing diagram for the ctc mode is shown in figure 23-3 on page 96 . the counter value (tcntn) increases until a compare match occurs between tcntn and o crna, and then counter (tcntn) is cleared. figure 23-3. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by us ing the ocfna flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low presca ler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna is lower th an the current value of tcntn, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x00. 23.5.3 16-bit mode in 16-bit mode, the counter (t cntnh/l) is a incrementing until it overruns w hen it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000), see table 23-2 on page 95 for bit settings. the overflow flag (tovn) will be set in the same timer clock cycle as the tcntnh/l becomes ze ro. the tovn flag in this ca se behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automat ically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the ou tput compare unit can be used to generate interrupts at some given time. 12 tcntn period 3 ocnx interrupt fl a g set 3 97 atmel ata9999 [datasheet] 8096c?avr?01/13 23.5.4 clear timer on compare match (ctc) 16-bit mode in clear timer on compare 16-bit mode, ocrana/b regist ers are used to manipulate the counter resolution, see table 23-2 on page 95 for bit settings. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches ocrna/b, where ocrnb represents the eight most si gnificant bits and ocrna represents th e eight least significant bits. ocrna/b defines the top value of the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. an interrupt can be generated each time t he counter reaches the top value by using th e ocfna flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the to p value. however, changing the top to a value close the bottom when the counter is running with none or a low presca ler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna/b is lower than the current value of tcntn, the counter will miss the compare match. the counter will then have to co unt to its maximum value (0xffff) and wrap around starting at 0x0000 before compare match can o ccur. as for the 16-bit mode, t he tovn flag is set in the sa me timer clock cycle that the counter counts from max to 0x0000. 23.5.5 8-bit input capture mode the timer/counter can be used in a 8-bit input capture mode, see table 23-2 on page 95 for bit settings. for full description, see section 23.6 ?input capture unit? on page 97 . 23.5.6 16-bit input capture mode the timer/counter can also be used in a 16-bit input capture mode, see table 23-2 on page 95 for bit settings. for full description, see section 23.6 ?input capture unit? on page 97 . 23.6 input capture unit the timer/counter incorporates an input c apture unit that can ca pture external events and give them a time-stamp indicating time of occurrence. the external signal indicates an event, or multiple events. for timer/counte r0, the event is triggered by completion of a cadc instantaneous conver sion (icp00) or completion of a cadc accumulated conversion (icp01). for timer/counter1, the events can be applied by the pb7 pin (icp10), by the lin rx comp lete signal (icp11) or by the lin tx complete signal (icp12). the time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 23-4 on page 97 . the elements of the block diagram that are not directly a part of th e input capture unit are gray shaded. figure 23-4. input capture unit block diagram icfn (int. req.) ocrna (8-bit) ocrnb (8-bit) icrn (16-bit register) temp (8-bit) tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data b u s (8-bit) noise c a nceler edge detector icpn1 icpn2 icsn icncn write icesn icpn0 98 atmel ata9999 [datasheet] 8096c?avr?01/13 the output compare register ocrna is a dual-purpose register t hat is also used as an 8-bit input capture register icrn. in 16-bit input capture mode the output compare register ocrnb serves as the high byte of the input capt ure register icrn. in 8-bit input capture mode the outp ut compare register ocrnb is free to be used as a normal output co mpare register, but in 16-bit input capture mode the output com pare unit cannot be used as there are no free output compar e register(s). even though the input capture register is called i crn in this section, it is referring to the output compare register(s). for more information on how to access the 16-bit registers refer to section 23.9 ?accessing registers in 16-bit mode? on page 102 . when a change of the logic level (an event) occurs on the input capture pin (icpx), and this change confirms to the setting of the edge detector, a capture will be triggered. when a capture is triggered, the value of the counter (tcntn) is written to the i nput capture register (icrn ). the input capt ure flag (icfn) is set at the same system clock as the tcntn value is copied into input capture register. if enabled (ticien=1), the input captur e flag generates an input capture interrupt. the icfn flag is automatically cleared when the interrupt is executed. alternatively the icfn flag can be cleared by software by writing a logic al one to its i/o bit location. 23.6.1 input capture trigger source the default trigger source for the input capture unit is the co mpletion of a cadc instantaneous conversion in timer/counter0 and the i/o port pb7 in timer/counter1. alternatively can the completion of cadc accumulated conversion event be used as trigger source for timer/counter0, and the lin rx and tx comp lete events be used as trigger sources for timer/counter1. the input capture trigger source s are selected as trigger sources by setting the in put capture select bits. be aware that changing trigger source can trigger a capture. the input capt ure flag must therefore be cleared after the change. both input capture inputs are sampled using the same technique. the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the e dge detector, which increases the de lay by four system clock cycl es. an input capture on timer/counter1 can also be triggered by software by controlling the port of the pb7 pin. 23.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changi ng the output that in turn is used by the edge detector. the noise canceler is enabled by setting the in put capture noise canceler (icncn) bit in section 23.10.1 ?tccrna ? timer/counter n control register a? on page 104 . when enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the u pdate of the icrn register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 23.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured va lue in the icrn register before the next event occurs, the icrn will be overwritt en with a new value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the interrupt handler routine as possible. the maximum interrupt response time is dependent on the maximu m number of clock cycles it takes to handle any of the other interrupt requests. measurement of an external signal duty cycl e requires that the trigger edge is chang ed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical on e to the i/o bit location). for measuring frequency only, the trig ger edge change is not required. 99 atmel ata9999 [datasheet] 8096c?avr?01/13 23.7 output compare unit the comparator continuously compares th e timer/counter (tcntn) with the output compare registers (ocrna and ocrnb), and whenever the timer/counter equals to the output compare regisers, the comparat or signals a match. a match will set the output compare flag at t he next timer clock cycle. in 8-bi t mode the match can set either th e output compare flag ocfna or ocfnb, but in 16-bit mode the match can set only the output compare flag ocfna as there is only one output compare unit. if the corresponding interrupt is enabled, the output comp are flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is ex ecuted. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. figure 23-5 on page 99 shows a block diagram of the output compare unit. figure 23-5. output compare unit, block diagram table 23-3. timer/counter0 input capture source (ics) ics[1:0] source 00 (1)(2) icp00: cadc instantaneous conversion complete interrupt 01 (1)(2) icp01: cadc accumulated conversion complete interrupt 10 reserved for future use 11 reserved for future use notes: 1. the noise canceler may filter out this source and it is therefore not recommende d to use noise canceler with this source. 2. if this interrupt is chosen as the input capture s ource, an input capture event will generate both the chosen interrupt and the input capture interrupt . if both interrupts are enabled, the sequence in which the interrupts are handled depends on a number of factors. the applicat ion software must therefore allow for both the input capture interrupt being handled before the chosen interr upt trigger, and after the chosen interrupt trigger. table 23-4. timer/counter1 input capture source (ics) ics[1:0] source 00 icp10: port pb7 01 (1)(2) icp11: lin rx complete interrupt 10 (1)(2) icp12: lin tx co mplete interrupt 11 reserved for future use notes: 1. the noise canceler may filter out this source and it is therefore not re commended to use noise canceler with this source. 2. if this interrupt is chosen as the input capture s ource, an input capture event will generate both the chosen interrupt and the input capture interrup t. if both interrupts are enabled, the sequence in which the interrupts are handled depends on a number of factors. the application so ftware must therefore allow for both the input cap- ture interrupt being handled before the chosen interrupt trigger, and after the chosen interrupt trigger. ocfnx (int. req.) = (8/16-bit comp a r a tor) ocrnx tcntn data b u s 100 atmel ata9999 [datasheet] 8096c?avr?01/13 23.7.1 compare match blocking by tcnt0 write all cpu write operations to the t cntnh/l register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocrna/b to be initialized to the same value as tcntn without triggering an interrupt when the timer/counter clock is enabled. 23.7.2 using the ou tput compare unit since writing tcntnh/l will block all compare matches for one timer clock cycle, there are risks involved when changing tcntnh/l when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcntnh/l equals the ocrna/b value, the compare match will be missed. 23.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 23-6 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value. figure 23-6. timer/counter timing diagram, no prescaling figure 23-7 shows the same timing data, but with the prescaler enabled. figure 23-7. timer/counter timing diagram, with prescaler (f clk_i/o /8) max - 1 clk i/o (clk i/o /1) tcntn tovn clk tn max bottom bottom + 1 max - 1 clk i/o (clk i/o /8) tcntn tovn clk tn max bottom bottom + 1 101 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 23-8 shows the setting of ocfna and ocfnb in normal mode. figure 23-8. timer/counter timing diagra m, setting of ocfnx, with prescaler (f clk_i/o /8) figure 23-9 shows the setting of ocfna and the clearing of tcntn in ctc mode. figure 23-9. timer/counter timing di agram, ctc mode, with prescaler (f clk_i/o /8) ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx v a lue ocrnx + 2 top - 1 clk pck (clk pck /8) tcntn (ctc) ocrnx ocfnx clk tn top bottom top bottom + 1 102 atmel ata9999 [datasheet] 8096c?avr?01/13 23.9 accessing registers in 16-bit mode in 16-bit mode (the tcwn bit is set to one) the tcntnh/l and ocrna/b or tcntnl/h and ocrn b/a are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-b it register must be byte a ccessed using two read or write operations. the 16-bit timer/counter has a single 8-bit register for temporary storing of the high byte of the 16-bit access. t he same temporary register is shared between all 16-bit registers. acce ssing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit regi ster is written by the cpu, the high byte stored in the temporary register, and th e low byte written are both copied into the 16-bi t register in the same clo ck cycle. when the low byte of a 16-bit register is re ad by the cpu, the high byte of the 16-bit regist er is copied into the temporary register in the same clock cycle as the low byte is read. there is one exception in the temporary register usage. in th e output compare mode the 16-bit output compare register ocrna/b is read without the temporary register, because the outp ut compare register contains a fixed value that is only changed by cpu access. however, in 16-bit input capture mode the icrn register formed by the ocrna and ocrnb registers must be accessed with the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before th e high byte. the following code examples show how to access the 16-bit time r registers assuming that no in terrupts updates the temporary register. the same principle can be used dire ctly for accessing the ocrna/b registers. the assembly code example returns the tcnt nh/l value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instruc tions accessing the 16-bit register, and the inte rrupt code updates the temporar y register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be co rrupted. therefore, when both the main co de and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code example ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code example unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... note: 1. see section 12. ?about code examples? on page 34 103 atmel ata9999 [datasheet] 8096c?avr?01/13 the following code examples show how to do an atomic read of the tcntn register contents. re ading any of the ocrn register can be done by using the same principle. the assembly code example returns the tcntnh/l value in the r17:r16 register pair. assembly code example timn_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example unsigned int timn_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } note: 1. see section 12. ?about code examples? on page 34 104 atmel ata9999 [datasheet] 8096c?avr?01/13 the following code examples show how to do an atomic write of the tcntnh/l register contents. writing any of the ocrna/b registers can be done by using the same principle. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcntnh/l. 23.9.1 reusing the temporary high byte register if writing to more than one 16-bit regist er where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of at omic operation described previously also applies in this case. 23.10 register description 23.10.1 tccrna ? timer/counter n control register a bit 7? tcwn: timer/counter width when this bit is written to one 16-bit mode is selected. ti mer/counter n width is set to 16-bits and the output compare registers ocrna and ocrnb are combined to form one 16-bit output compare register. because the 16-bit registers tcntnh/l and ocrnb/a are accessed by the avr cpu via the 8-bit data bus, special procedures must be followed. these procedures are described in section 23.9 ?accessing registers in 16-bit mode? on page 102 . bit 6? icenn: input capture mode enable the input capture mode is enabled when this bit is written to one. assembly code example timn_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example void timn_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } note: 1. see section 12. ?about code examples? on page 34 bit 76543210 tcwn icenn icncn icesn ? ? ? wgmn0 tccrna read/write r/w r/w r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 105 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 5 ? icncn: input capture noise canceler setting this bit activates the input capture noise canceler. when the noise canceler is activa ted, the input from the input capture source is filtered. the filter function requires four successive equal valued samples of the input capture source for changing its output. the input capture is therefore delayed by four system clock cycles when the noise canceler is enabled. bit 4 ? icesn: input capture edge select this bit selects which edge on the input c apture source that is used to trigger a capture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the icesn setting, the counter va lue is copied into the input capture register. the event will also set the input capture flag (icf n), and this can be used to cause an input capture interrupt, if this interrupt is enabled. bits 3 ? reserved this bit is reserved in the atmel ? avr mcu and should always be written to zero. bits 2:1 ? reserved these bits are reserved bits in the avr mcu and will always read as zero. bit 0 ? wgmn0: waveform generation mode this bit controls the counting sequence of the counte r, the source for maximum (top) counter value, see figure 23-6 on page 100 . modes of operation supported by the timer/counter unit are: normal mode (counter) and clear timer on compare match (ctc) mode (see section 23.8 ?timer/counter timing diagrams? on page 100 ). 23.10.2 tccrnc ? timer/counter n control register c bit 7:2 ? reserved these bits are reserved bits in the atmel ? avr mcu and will always read as zero. bit 1:0 ? ics[1:0]: input capture select 1:0 these bits control which input capture source that should tr igger the timer/counter input capture functionality. to also trigger the timer/counter n input capture interrupt, the ticien bit in the ti mer interrupt mask register timsk) must be set. see table 23-3 on page 99 and table 23-4 on page 99 for input capture sources. 23.10.3 tcntnl ? timer/counter n register low byte the timer/counter register tcntnl gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcntnl register blocks (disables) the compare match on the following timer clock. modifying the counter (tcntnl) while the counter is running, introduces a risk of missing a compare match between tcntnl and the ocrnx registers. in 16-bit mode the tcntnl register contai ns the lower part of the 16-b it timer/counter n register. bit 76543210 ? ? ? ? ? ? icn1 icn0 tccrnc read/writerrrrrrr/wr/w initial value00000000 bit 76543210 tcntnl[7:0] tcntnl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 106 atmel ata9999 [datasheet] 8096c?avr?01/13 23.10.4 tcntnh ? timer/counter n register high byte when 16-bit mode is selected (the tcwn bit is set to one) the timer/counter register tcntnh combined to the timer/counter register tcntnl gives direct access, both for read and write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simult aneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registe rs. see section 23.9 ?accessing registers in 16-bit mode? on page 102 . 23.10.5 ocrna ? timer/counter n output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcntnl). a match can be used to generate an output compare interrupt. in 16-bit mode the ocrna register contains the low byte of the 16-bit output compare register. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary regi ster is shared by all the other 16-bit registers. see section 23.9 ?accessing registers in 16-bit mode? on page 102 . 23.10.6 ocrnb ? timer/counter n output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcntnl in 8-bit mode and tcntnh in 16-bit mode). a match can be used to generate an output compare interrupt. in 16-bit mode the ocrnb register contains the high byte of the 16-bit output compare register. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary regi ster is shared by all the other 16-bit registers. see section 23.9 ?accessing registers in 16-bit mode? on page 102 . 23.10.7 timskn ? timer/counter n interrupt mask register bit 3 ? icien: timer/counter n input capture interrupt enable when this bit is written to one, and the i- flag in the status register is set (inte rrupts globally enabled), the timer/counter n input capture interrupt is enabled. the corresponding interrupt vector (see section 19. ?interrupts? on page 70 ) is exe- cuted when the icfn flag, located in tifrn, is set. bit 2 ? ocienb: timer/counter n outp ut compare match b interrupt enable when the ocienb bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding in terrupt is executed if a compare match in timer/counter occurs, i.e., when the ocfnb bit is set in the timer/counter interrupt flag register ? tifrn. bit 76543210 tcntnh[7:0] tcntnh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ocrna[7:0] ocrna read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocrnb[7:0] ocrnb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? icien ocienb ociena toien timskn read/writerrrrr/wr/wr/wr initial value00000000 107 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 1 ? ociena: timer/co unter n output compare match a inte rrupt enable when the ociena bit is written to one, and the i-bit in the status register is set, the timer/counter n compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter n occu rs, i.e., when the ocfna bit is set in the timer/counter n interrupt flag register ? tifrn. bit 0 ? toien: timer/counter n overflow interrupt enable when the toien bit is written to one, and t he i-bit in the status register is set, the timer/counter n overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter n occurs, i. e., when the tovn bit is set in the timer/counter n interrupt flag register ? tifrn. 23.10.8 tifrn ? timer/counter n interrupt flag register bits 3 ? icfn: timer/counter n input capture flag this flag is set when a capture event occurs, according to th e setting of icenn, icesn and icsn[1:0] bits in the tccrna and tccrnc registers. icfn is automatically cleared when the input capture interrupt vector is executed. alternatively, icfn can be cleared by writing a logic one to its bit location. bit 2 ? ocfnb: output compare flag n b the ocfnb bit is set when a compare match occurs between the timer/counter and the da ta in ocrnb ? output com- pare register n b. ocfnb is cleared by hardware wh en executing the corresponding interrupt handling vector. alternatively, ocfnb is cleared by writing a logic one to the flag. when the i-bit in sreg, ocienb (timer/counter com- pare b match interrupt enable), and ocfnb are set, t he timer/counter compare match interrupt is executed. the ocfnb is not set in 16-bit output compare mode when the output compare register ocrnb is used as the high byte of the 16-bit output compare register or in 16-bit input capture mode when the output compare register ocrnb is used as the high byte of the input capture register. bit 1? ocfna: output compare flag n a the ocfna bit is set when a compare match occurs between the timer/counter n and the data in ocrna ? output compare register n. ocfna is cleared by hardware when executing the corresponding interrupt handling vector. alter- natively, ocfna is cleared by writing a logic one to the fl ag. when the i-bit in sreg, ociena (timer/counter n compare match interrupt enable), and ocfna are set, the ti mer/counter n compare match interrupt is executed. the ocfna is also set in 16-bit mode when a compare match occurs between the timer/counter n and 16-bit data in ocrnb/a. the ocfna is not set in input capture mode when the output compare register ocrna is used as an input capture register. bit 0 ? tovn: timer/c ounter n overflow flag the bit tovn is set when an overflow occurs in timer/count er n. tovn is cleared by har dware when executing the cor- responding interrupt handling vector. alternatively, tovn is cleared by writing a logic one to the flag. when the sreg i- bit, toien (timer/counter n overflow interrupt enable), and tovn are set, the timer/count er n overflow interrupt is executed. bit 76543210 ? ? ? ? icfn ocfnb ocfna tovn tifrn read/write r r r r r/w r/w r/w r/w initial value00000000 108 atmel ata9999 [datasheet] 8096c?avr?01/13 24. spi ? serial peripheral interface 24.1 features full-duplex, three-wire synchronous data transfer master or slave operation lsb first or msb first data transfer seven programmable bit rates end of transmission interrupt flag write collision protection flag wake-up from idle mode double speed (ck/2) master spi mode 24.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the atmel ? avr mcu and peripheral devices or between several avr devices. when the spi is not used, power consumption can be mini mized by writing the prspi bit in prr0 to one. see section 16.7.2 ?prr0 ? power reduction register 0? on page 57 for details on how to use the prspi bit. figure 24-1. spi block diagram (1) note: 1. refer to ?alternate port functions? on page 83 for spi pin placement. 8-bit shift register re a d d a t a buffer spi control register spi st a tus register mstr spi clock (m a ster) spe spi control spi interrupt request select clock logic miso clock 8 88 s m s m m s msb lsb spie spe wcol spif spi2x spi2x spr1 mstr spe dord spr0 dord mstr cpol cpha spr1 spr0 mosi sck ss divider /2/4/8/16/32/64/128 xtal intern a l d a t a bus pin control logic 109 atmel ata9999 [datasheet] 8096c?avr?01/13 the interconnection between master a nd slave cpus with spi is shown in figure 24-2 . the system consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective sh ift registers, and the master generates the required clock pulses on the sck line to interchang e data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi inte rface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifti ng one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into sp dr, or signal the end of packet by pulling high the slave selec t, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will rema in sleeping with miso tri- stated as long as the ss pin is driven high. in this state, software may update the content s of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interru pt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 24-2. spi master-slave interconnection the system is single buffered in the transmi t direction and d ouble buffered in the receive dire ction. this means that bytes to be transmitted cannot be written to the spi da ta register before the entire shift cycle is completed. when receiving data, however , a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming si gnal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f osc /4. when the spi is enabled, the data direct ion of the mosi, miso, sck, and ss pins is overridden according to table 24-1 on page 109 . for more details on automatic port overrides, refer to section 21.3 ?alternate port functions? on page 83 . table 24-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input note: 1. see section 21.3.2 ?alternate functi ons of port b? on page 86 for a detailed description of how to define the direction of the user defined spi pins. lsb slave msb 8 bit shift register lsb shift en a ble master msb ss sck ss sck mosi mosi miso miso 8 bit shift register spi clock gener a tor 110 atmel ata9999 [datasheet] 8096c?avr?01/13 the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by the actual data directi on register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for th ese pins. e.g., if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 113 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 24-3. spi transfer format with cpha = 0 figure 24-4. spi transfer format with cpha = 1 lsb msb bit 1 bit 6 bit 2 bit 5 bit 3 bit 4 bit 4 bit 3 bit 5 bit 2 bit 6 bit 1 msb lsb msb first (dord = 0) lsb first (dord =1) sck (cpol = 0) mode 0 sck (cpol = 1) mode 2 ss sample - mosi/miso change 0 mosi pin change 0 miso pin lsb msb bit 1 bit 6 bit 2 bit 5 bit 3 bit 4 bit 4 bit 3 bit 5 bit 2 bit 6 bit 1 msb lsb msb first (dord = 0) lsb first (dord =1) sck (cpol = 0) mode 1 sck (cpol = 1) mode 3 ss sample - mosi/miso change 0 mosi pin change 0 miso pin 114 atmel ata9999 [datasheet] 8096c?avr?01/13 24.5 register description 24.5.1 spcr ? spi control register bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and the if th e global interrupt enable bit in sreg is set. bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. bit 5 ? dord: data order when the dord bit is written to one, the l sb of the data word is transmitted first. when the dord bit is written to zero, the m sb of the data word is transmitted first. bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. wh en cpol is written to zero, sck is low when idle. refer to fig- ure 24-3 and figure 24-4 for an example. the cpol functionality is summarized below. bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 24-3 and figure 24-4 for an example. the cpha functionality is summarized below. bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 24-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 24-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample 115 atmel ata9999 [datasheet] 8096c?avr?01/13 bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: 24.5.2 spsr ? spi status register bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global inter- rupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the correspondi ng interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi st atus register with wcol set, and t hen accessing the spi data register. bit 5:1 ? reserved these bits are reserved bits in the atmel ? avr mcu and will always read as zero. bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck frequen cy) will be doubled when the spi is in master mode (see table 24-5 on page 115 ). this means that the minimum sck period will be two cpu clock periods. when the spi is con- figured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmel avr mcu is also used for program memory and eeprom downloading or uploading. see table 30.6 on page 183 for serial programmi ng and verification. 24.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register fi le and the spi shift register. writing to the register initiate s data transmission. reading the register causes the shift register receive buffer to be read. table 24-5. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 0 0 0 f osc / 4 0 0 1 f osc / 16 0 1 0 f osc / 64 0 1 1 f osc / 128 1 0 0 f osc / 2 1 0 1 f osc / 8 1 1 0 f osc / 32 1 1 1 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/writerrrrrrrr/w initial value00000000 bit 76543210 0x2e (0x4e) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 116 atmel ata9999 [datasheet] 8096c?avr?01/13 25. lin/uart 25.1 features single master with multiple slaves concept low cost silicon implementation ba sed on common uart/sci interface self synchronization with on-chip oscillator in slave node deterministic signal transmission with signal propagation time computable in advance low cost single-wire implementation 25.2 overview the lin (local interconnect network) is a serial communications protocol which efficiently suppo rts the control of mechatronics nodes in distributed automotive applications. lin provides a cost efficient bus communication where the band width and versatility of can ar e not required. if lin is not required, the controller alternatively can be programmed as un iversal asynchronous serial receiver and transmitter (uart). 25.3 lin features hardware implementation of lin 2.1 (lin 1.3 compatibility) small, cpu efficient and independent master /slave routines based on ?lin work fl ow concept? of li n 2.1 specification automatic lin header handling and filtering of irrelevant lin frames automatic lin re sponse handling extended lin error detection and signaling hardware frame time-out detection automatic re-synchronization to ensure proper frame integrity fully flexible extended frames support capabilities 25.4 uart features full duplex operation (independent serial receive and transmit processes) asynchronous operation high resolution baud rate generator hardware support of 8 data bits, odd/even/no parity bit, 1 stop bit frames data over-run and framing error detection 117 atmel ata9999 [datasheet] 8096c?avr?01/13 25.5 lin protocol 25.5.1 master and slave a lin cluster consists of one master task and several slave tasks . a master node contains the master task as well as a slave task. all other nodes contain a slave task only. figure 25-1. lin cluster with one master node and ?n? slave nodes the master task decides when and which fr ame shall be transferred on the bus. the sl ave tasks provide the data transported by each frame. both the master task and th e slave task are parts of the frame handler 25.5.2 frames a frame consists of a header (provided by the master task) and a response (provided by a slave task). the header consists of a break and sync pattern followed by a protected identifier. the identifier uni quely defines the purpose of the frame. the slave task appointed for providing the response associated with the identifier transmits it. the response consists of a dat a field and a checksum field. figure 25-2. master and slave tasks behavior in lin frame the slave tasks waiting for the data associat ed with the ident ifier receives the response and uses the data tr ansported after verifying the checksum. figure 25-3. structure of a lin frame m a ster t a sk ma s ter node sl a ve t a sk s lave node 1 lin bu s sl a ve t a sk s lave node n sl a ve t a sk header m a ster t a sk sl a ve t a sk 1 sl a ve t a sk 2 response header response field field sync header frame slot response bre a k delimiter break field protected identifier field data 0 field data n checksum field inter byte sp a ce inter fr a me sp a ce e a ch byte field is tr a nsmitted a s a seri a l byte, lsb first response sp a ce 118 atmel ata9999 [datasheet] 8096c?avr?01/13 25.5.3 data transport two types of data may be transported in a frame; signals or diagnostic messages. signals signals are scalar values or byte arrays that are packed into the data field of a frame. a signal is always present at the same position in the data field for all frames with the same identifier. diagnostic messages diagnostic messages are transported in frames with two reserved identifiers. the interpretation of the data field depends on the data field itself as well as t he state of the communicating nodes. 25.5.4 schedule table the master task (in the master node) trans mits frame headers based on a schedule table. the schedule table specifies the identifiers for each header and the interval between the start of a frame and the start of the following frame. the master application may use different schedul e tables and select among them. 25.5.5 compatibility with lin 1.3 lin 2.1 is a super-set of lin 1.3. a lin 2.1 master node can handle clusters consisting of both li n 1.3 slaves and/or lin 2.1 slaves. the master will then avoid requesting the new lin 2.1 features from a lin 1.3 slave: enhanced checksum, re-configuration and diagnostics, automatic baud rate detection, "response error" status monitoring. lin 2.1 slave nodes can not operate with a lin 1.3 master node (e.g., the lin1.3 master does not support the enhanced checksum). the lin 2.1 physical layer is backwards compatible with the li n1.3 physical layer. but not t he other way around. the lin 2.1 physical layer sets greater requirements, i.e. a master node us ing the lin 2.1 physical layer can operate in a lin 1.3 cluster. 25.6 lin / uart controller the lin/uart controller is divided in three main functions: tx lin header function, rx lin header function, lin response function. these functions mainly use two services: rx service, tx service. because these two services are basically uart services, the controller is also able to switch into an uart function. 25.6.1 lin overview the lin/uart controller is designed to match as closely as possi ble to the lin software applicat ion structure. the lin software application is developed as independent tasks, several slave tasks and one master task (c.f. section 25.5.4 on page 118 ). the atmel ? avr mcu conforms to this perspective. the only link between the master task and the slave task will be at the cross- over point where the interrupt routine is called once a new identifier is available. thus, in a master node, housing both maste r and slave task, the tx lin header function will alert the slave ta sk of an identifier presence. in the same way, in a slave nod e, the rx lin header function will alert the slave task of an identifier presence. when the slave task is warned of an identif ier presence, it has first to analyze it to know what to do with the response. hardw are flags identify the presence of on e of the specific identifiers from 60 (0x3c) up to 63 (0x3f). 119 atmel ata9999 [datasheet] 8096c?avr?01/13 for lin communication, only four interrupts need to be managed: lidok: new lin identifier available, lrxok: lin response received, ltxok: lin response transmitted, lerr: lin error(s). the wake-up management can be automated using the uart wake-up capability and a node sending a minimum of 5 low bits (0xf0) for lin 2.1 and 8 low bits (0x80) for lin 1.3. pin chan ge interrupt on lin wake-up signal can be also used to exit the device of one of its sleep modes. extended frame identifiers 62 (0x3e) and 63 (0x3f) are rese rved to allow the embedding of user-defined message formats and future lin formats. the byte transfer m ode offered by the uart will ensure the upwards compatibility of lin slaves with accommodation of the lin protocol. 25.6.2 uart overview the lin/uart controller can al s o f u nction a s a conventional uart. by defa u lt, the uart operate s a s a f u ll d u plex controller. it ha s local loop b ack circ u itry for te s t p u rpo s e s . the uart ha s the a b ility to b u ffer one character for tran s mit and two for receive. the receive b u ffer i s made of one 8 - b it s erial regi s ter followed b y one 8 - b it indepen- dent b u ffer regi s ter. a u tomatic flag management i s implemented when the application p u t s or get s character s , th us red u cing the s oftware overhead. beca us e tran s mit and receive s ervice s are independent, the us er can s ave one device pin when one of the two s ervice s i s not us ed. the uart ha s an enhanced b a u d rate generator providing a maxim u m error of 2% whatever the clock fre qu ency and the targeted b a u d rate. the b a u d rate i s given b y: 25.6.3 lin/uart cont roller structure figure 25-4. lin/uart controller block diagram uart baud rate lin/uart clock freqency (linbtr (lindiv 1)) + ------------------------------------------------------------------- = presc a ler clk i/o rxd s a mple /bit baud_rate get byte rx fr a me time out synchroniz a tion monitoring d a t a fifo put byte tx finite st a te m a chine fsm buffer 120 atmel ata9999 [datasheet] 8096c?avr?01/13 25.6.4 lin/uart command overview figure 25-5. lin/uart command dependencies table 25-1. lin/uart command list lena lcmd[2] lcmd[1] lcmd[0] command comment 0 x x x disable peripheral 1 0 0 0 rx header - lin abort lin withdrawal 1 tx header lcmd[2..0]=000 after tx 1 0 rx response lcmd[2..0]=000 after rx 1 tx response lcmd[2..0]=000 after tx 1 0 0 byte transfer no crc, no time out ltxdl=lrxdl=0 (lindlr: read only register) 1 0 rx byte 0 1 tx byte 1 1 full duplex rx he a der or lin abort byte tr a nsfer disable lin uart tx response idok recommended w a y txok rxok rx byte tx response tx byte tx he a der full duplex possible w a y autom a tic return 121 atmel ata9999 [datasheet] 8096c?avr?01/13 25.6.5 enable/disable setting the lena bit in lincr register en ables the lin/uart controller. to disable the lin/uart controller, lena bit must be written to 0. no wait states are implemented, so, th e disable command is taken into account immediately. 25.6.6 lin commands clearing the lcmd[2] bit in lincr register enables lin commands. as shown in table 25-1 on page 120 , four functions controlled by the lcmd[1..0] bits of lincr register are available (c.f. figure 25-5 on page 120 ). 25.6.6.1rx header/lin abort function this function (or state) is mainly the withdrawal mode of the controller. when the controller has to execute a mast er task, this state is the start poin t before enabling a tx header command. when the controller has only to execute slave tasks, lin header de tection/acquisition is enabled as background function. at the end of such an acquisition (rx header func tion), automatically the appr opriate flags are set, and in lin 1.3, the lindlr regist er is set with the uncoded length value. this state is also the start point before enabling the tx or the rx response command. a running function (i.e. tx header, tx or rx response) can be aborted by clearing lcmd[1..0] bits in lincr register. in this case, an abort flag - labort - in linerr register will be set to inform the other software tasks. no wait states are implemented, so, the abor t command is taken into account immediately. rx header function is responsible for: the break field detection, the hardware re-synchronization analyzing the synch field, the reception of the protected identifier field, the parity control and the update of the li ndlr register in case of lin 1.3, the starting of the frame_time_out, the checking of the lin communication integrity. 25.6.6.2tx header function in accordance with the lin protocol, only th e master task must enable this function. t he header is sent in the appropriate time d slots at the programmed baud rate (c.f. linbrr and linbtr registers). the controller is responsible for: the transmission of the break field - 13 dominant bits, the transmission of the synch field - character 0x55, the transmission of the protected identifier field. it is the full content of the linidr register (automatic check bits included). at the end of this transmission, the controller automatically returns to rx header / lin abort state (i.e. lcmd[1..0] = 00) after setting the appropriate flags. this function leaves the controller in the same setting as after the rx header function. this means that, in lin 1.3, the lindlr register is set with the uncoded length value at the end of the tx header function. during this function, the controller is also responsible for: the starting of the frame_time_out, the checking of the lin communication integrity. 122 atmel ata9999 [datasheet] 8096c?avr?01/13 25.6.6.3rx and tx response functions these functions are initiated by the slave task of a lin node. they must be used after sending an header (master task) or after receiving an header (considered as belonging to the slave task) . when the tx response order is sent, the transmission begins. a rx response order can be sent up to the reception of th e last serial bit of the first byte (before the stop-bit). in lin 1.3, the header slot configures th e lindlr register. in lin 2.1, the user must configure the li ndlr register, either lrxdl[3..0] for rx response either ltxdl[3..0] for tx response . when the command starts, the c ontroller checks the lin13 bit of the lincr regist er to apply t he right rule for computing the checksum. checksum calcul ation over the data bytes a nd the protected identifier by te is called enhanced checksum and it is used for communicat ion with lin 2.1 slaves. che cksum calculation over the data bytes only is called classic checksum and it is used for communication with lin 1.3 slaves. note that identifiers 60 (0x3c) to 63 (0x3f) shall always use classic checksum. at the end of this reception or transmission , the controller automatically returns to rx header / lin abort state (i.e. lcmd[1..0] = 00) after setting the appropriate flags. if an lin error occurs, the reception or t he transmission is stopped, the appropriate fl ags are set and the lin bus is left to recessive state. during these functions, the controller is responsible for: the initialization of the checksum operator, the transmission or the reception of ?n? data with the update of the checksum calculation, the transmission or the checking of the checksum field, the checking of the frame_time_out, the checking of the lin communication integrity. while the controller is sending or receiving a response, break and synch fields can be detected and the identifier of this new header will be recorded. of course, specific errors on the prev ious response will be maintained with this identifier reception. 25.6.6.4handling da ta of lin response a fifo data buffer is used for data of the lin response. afte r setting all parameters in the linsel register, repeated accesses to the lindat register perform data read or data write (c.f. section 25.7.13 ?data management? on page 131 ). note that lrxdl[3..0] and ltxdl[3..0] are not linked to the data access. 25.6.7 uart commands setting the lcmd[2] bit in linenr register enables uart commands. tx byte and rx byte services are independent as shown in table 25-1 on page 120 . byte transfer: the uart is selected but both rx and tx services are disabled, rx byte: only the rx service is enable but tx service is disabled, tx byte: only the tx service is enable but rx service is disabled, full duplex: the uart is selected and both rx and tx services are enabled. this combination of services is controlled by the lcmd[1..0] bits of linenr register (c.f. figure 25-5 on page 120 ). 25.6.7.1data handling the fifo used for lin communication is disabled during uart accesses. lrxdl[3..0] and ltxdl[3..0] values of lindlr register are then irrelevant. lindat register is then used as data register and linsel register is not relevant. 123 atmel ata9999 [datasheet] 8096c?avr?01/13 25.6.7.2rx service once this service is enabled, the user is warned of an in-c oming character by the lrxok fl ag of linsir register. reading lindat register automatically clears the flag and makes free the second stage of the buffer. if the user considers that the in- coming character is irrelevant without reading it, he directly can clear the flag (see specific flag management described in section 25.8.2 on page 133 ). the intrinsic structure of the rx service of fers a 2-byte buffer. the fist one is used for serial to parallel conversion, the s econd one receives the result of the conversion. this second buffer byte is reached reading lindat register. if the 2-byte buffer is full, a new in-coming character will overwrite the second one already recorded. an ov rerr error in linerr register will then accompany this character when read. a ferr error in linerr register will be set in case of framing error. 25.6.7.3tx service if this service is enabled, the user sends a character by writi ng in lindat register. automatically the ltxok flag of linsir register is cleared. it will rise at the end of the serial transmission. if no new character has to be sent, ltxok flag c an be cleared separately (see spec ific flag management described in section 25.8.2 on page 133 ). there is no transmit buffering. no error is detected by this service. 25.7 lin / uart description 25.7.1 reset the avr core reset logic signal also resets the lin/uart contro ller. another form of reset exists, a software reset controlled by lswres bit in lincr register. this self-reset bit performs a partial reset as shown in table 25-2 . 25.7.2 lin protocol selection lin13 bit in lincr register is us ed to select the lin protocol: lin13 = 0 (default): lin 2.1 protocol, lin13 = 1: lin 1.3 protocol. the controller checks the lin13 bit in computing the checksum (enhanced checksum in lin2.1 / classic checksum in lin 1.3). this bit is irrelevant for uart commands. table 25-2. reset of lin/uart registers register name reset value lswres value comment lin control reg. lincr 0000 0000 b 0000 0000 b x=unknown u=unchanged lin status and interrupt reg. linsir 0000 0000 b 0000 0000 b lin enable interrupt reg. linenir 0000 0000 b xxxx 0000 b lin error reg. linerr 0000 0000 b 0000 0000 b lin bit timing reg. linbtr 0010 0000 b 0010 0000 b lin baud rate reg. low linbrrl 0000 0000 b uuuu uuuu b lin baud rate reg. high linbrrh 0000 0000 b xxxx uuuu b lin data length reg. lindlr 0000 0000 b 0000 0000 b lin identifier reg. linidr 1000 0000 b 1000 0000 b lin data buffer selection linsel 0000 0000 b xxxx 0000 b lin data lindat 0000 0000 b 0000 0000 b 124 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.3 configuration depending on the mode (lin or uart), lconf[ 1..0] bits of the lincr register set the controller in the following configuration ( table 25-3 ): the lin configuration is independent of the programmed lin protocol. the listening mode connects the internal tx lin and the internal rx lin together. in this mode, the txlin output pin is disable d and the rxlin input pin is always enabled. the same scheme is available in uart mode. figure 25-6. listening mode 25.7.4 busy signal lbusy bit flag in linsir register is the im age of the busy signal. it is set and clea red by hardware. it signals that the contro ller is busy with lin or uart communication. 25.7.4.1busy signal in lin mode figure 25-7. busy signal in lin mode table 25-3. configuration table versus mode mode lconf[1..0] configuration lin 00 b lin standard configuration (default) 01 b no crc field detection or transmission 10 b frame_time_out disable 11 b listening mode uart 00 b 8-bit data, no parity and 1 stop-bit 01 b 8-bit data, even parity and 1 stop-bit 10 b 8-bit data, odd parity and 1 stop-bit 11 b listening mode, 8-bit data, no parity and 1 stop-bit 0 1 intern a l tx lin intern a l rx lin listen rxlin txlin field field sync node providing the m a ster t a sk node providing a sl a ve t a sk header lin bus 1) lbusy 2) lbusy 3) lbusy frame slot response lcmd = tx he a der lidok lcmd = tx or rx response lidok or lrxok break field protected identifier field data 0 field data n checksum field node providing neither the m a ster t a sk, neither a sl a ve t a sk 125 atmel ata9999 [datasheet] 8096c?avr?01/13 when the busy signal is set, some registers are lock ed, user writing is not allowed: ?lin control register? - lincr - ex cept lcmd[2..0], lena and lswres, ?lin baud rate registers? - linbrrl and linbrrh, ?lin data length register? - lindlr, ?lin identifier register? - linidr, ?lin data register? - lindat. if the busy signal is set, the only available commands are: lcmd[1..0] = 00 b , the abort command is taken into account at the end of the byte, lena = 0 and/or lcmd[2] = 0, the kill comm and is taken into account immediately, lswres = 1, the reset command is taken into account immediately. note that, if another command is entered during busy signal, th e new command is not validated and the lovrerr bit flag of the linerr register is set. the on-going transf er is not interrupted. 25.7.4.2busy signal in uart mode during the byte transmission, the bu sy signal is set. this locks some registers from being written: ?lin control register? - lincr - ex cept lcmd[2..0], lena and lswres, ?lin data register? - lindat. the busy signal is not generated during a byte reception. 25.7.5 bit timing 25.7.5.1baud ra te generator the baud rate is defined to be the transfer rate in bits per second (bps): baud: baud rate (in bps), fclk i/o : system i/o clock frequency, ldiv[11..0]: contents of linbrrh and linbrrl r egisters - (0-4095), the pre-scaler receives clk i/o as input clock. lbt[5..0]: least significant bits of - linbtr register- (0-63) is the number of samplings in a lin or uart bit (default value 32). equation for calculating baud rate: baud = f clk i/o / lbt[5..0] x (ldiv[11..0] + 1) equation for setting lindiv value: ldiv[11..0] = ( f clk i/o / lbt[5..0] x baud ) - 1 note that in reception a majority vote on th ree samplings is made. 25.7.5.2re-synchroni zation in lin mode when waiting for rx header, lbt[5..0] = 32 in linbtr register. the re-synchroniza tion begins when the break is detected. if the break size is not in the rang e (11 bits min., 28 bits max. ? 13 bits nomin al), the break is refused. the re-synchronization is done by adjusting lbt[5..0] value to the synch field of the received header (0x 55). then the protected identifier is sampled using the new value of lbt[5..0]. the re-synchronization implemented in the controller tolerates a clock deviation of 20% and adjusts the baud rate in a 2% range. the new lbt[5..0] value will be used up to the end of the respon se. then, the lbt[5..0] will be reset to 32 for the next header . 126 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.5.3handli ng lbt[5..0] ldisr bit of linbtr register is used to: disable the re-synchronization (for instance in the case of lin master node), to enable the setting of lbt[5..0] (to manually adjust the baud rate especially in the case of uart mode). a minimum of 8 is required for lbt[5..0] due to the sampling operation. note that the lena bit of lincr register is important for this handling (see figure 25-8 on page 126 ). figure 25-8. handling lbt[5..0] 25.7.6 data length section 25.6.6 ?lin commands? on page 121 describes how to set or how are automatic ally set the lrxdl[3..0] or ltxdl[3..0] fields of lindlr register before re ceiving or transmitting a response. in the case of tx response the lrxdl[3..0] will be used by the hardware to count the numbe r of bytes already successfully sent. in the case of rx response the ltxdl[3..0] will be used by the hardware to count the numbe r of bytes already successfully received. if an error occurs, this informati on is useful to the programmer to recover the lin messages. 25.7.6.1data leng th in lin 2.1 if ltxdl[3..0]=0 only the checksum will be sent, if lrxdl[3..0]=0 the first byte receiv ed will be interpreted as the checksum, if ltxdl[3..0] or lrxdl[3..0] >8, values will be forced to 8 after the command setting and before sending or receiving of the first byte. 25.7.6.2data leng th in lin 1.3 lrxdl and ltxdl fields are both hardware updated before setti ng lidok by decoding the data length code contained in the received protected identifier (lrxdl = ltxdl). via the above mechanism, a length of 0 or >8 is not possible. lena ? (lincr bit4) ldi s r to write = 1 = 1 = 0 = 0 write in linbtr register lbt [5 to 0] forced to 0x20 ldi s r forced to 0 enable re-synch. in lin mode lbt [5 to 0] = lbt [5 to 0] to write (lbt [5 to 0] min = 8) ldi s r forced to 1 di s able re-synch. in lin mode 127 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.6.3data length in rx response figure 25-9. lin2.1 - rx response - no error the user initializes lrxdl field bef ore setting the rx response command, after setting the rx response command, ltxdl is reset by hardware, lrxdl field will remain unchanged during rx (during busy signal), ltxdl field will count the number of received bytes (during busy signal), if an error occurs, rx stops, the corresponding error flag is set and ltxdl will give the number of received bytes without error, if no error occurs, lrxok is set after the reception of the checksum, lrxdl will be unchanged (and ltxdl = lrxdl). 25.7.6.4data length in tx response figure 25-10.lin1.3 - tx response - no error the user initializes ltxdl field befo re setting the tx response command, after setting the tx response command, lrxdl is reset by hardware, ltxdl will remain unchanged during tx (during busy signal), lrxdl will count the number of transmitted bytes (during busy signal), if an error occurs, tx stops, the corresponding error flag is set and lrxdl will give the number of transmitted bytes without error, if no error occurs, ltxok is set after the transmis sion of the checksum, ltxdl will be unchanged (and lrxdl = ltxdl). data-0 lcmd = rx response lcmd2 to 0 = 000 b lindlr = 0x?4 ( * ): lrxdl a nd ltxdl upd a ted by user 4 ?01234 lidok lin bus lrxdl ( * ) ltxdl ( * ) lbusy 1 st byte 2 nd byte 3 rd byte 4 th byte lrxok data-1 data-2 data - 3 checksum data-0 lcmd = tx response lcmd2 to 0 = 000 b ( * ): lrxdl a nd ltxdl upd a ted by rx response or tx response t a sk 4 40 1 2 3 4 lidok lin bus lrxdl ( * ) ltxdl ( * ) lbusy 1 st byte 2 nd byte 3 rd byte 4 th byte lt x o k data-1 data-2 data - 3 checksum 128 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.6.5data leng th after error figure 25-11.tx response - error note: information on response (ex: error on byte) is only avail able at the end of the serializ ation/de-serialization of the byte. 25.7.6.6data leng th in uart mode the uart mode forces lrxdl and ltxdl to 0 and disables the writing in lindlr register, note that after reset, lrxdl and ltxdl are also forced to 0. 25.7.7 xxok flags there are three xxok flags in linsir register: lidok: lin identifier ok it is set at the end of the header, eit her by the tx header function or by the rx header. in lin 1.3, before generating lidok, the controller updates the lrxdl and ltxdl fields in lindlr register. it is not driven in uart mode. lrxok: lin rx response complete it is set at the end of the response by the rx response function in lin mode and once a character is received in uart mode. ltxok: lin tx response complete it is set at the end of the response by the tx response function in lin mode and once a character has been sent in uart mode. these flags can generate interrupts if the corresponding en able interrupt bit is set in the linenir register (see section 25.7.11 ?interrupts? on page 130 ). data-0 lcmd = tx response lcmd2 to 0 = 000 b 4 40 1 2 lin bus lrxdl ltxdl lbusy 1 st byte 2 nd byte 3 rd byte lerr data - 1 data - 2 error 129 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.8 xxerr flags lerr bit of the linsir register is an logical ?or? of all the bits of linerr register (see section 25.7.11 ?interrupts? on page 130 ). there are eight flags: lberr = lin bit error. a unit that is sending a bit on the bus also monitors the bus. a lin bit error will be flagged when the bit value that is monitored is different from the bit val ue that is sent. after detection of a li n bit error the transmission is aborted. lcerr = lin checksum error. a lin checksum error will be flagged if the inverted modulo- 256 sum of all received data bytes (and the protected identifier in lin 2.1) added to the checksum does not result in 0xff. lperr = lin parity error (identifier). a lin parity error in the identifier field will be flagged if th e value of the parity bits does not match with the identifier value. (see lp[1:0] bits in section 25.8.8 ?linidr ? lin ident ifier register? on page 136 ). a lin slave application does not distinguish between corrupted parity bits and a corrupted identifier. the hardware does not undertake any correction. however, the lin slave application has to solve this as: - known identifier (parity bits corrupted), - or corrupted identifier to be ignored, - or new identifier. lserr = lin synchronization error. a lin synchronization error will be flagged if a slave detects the edges of the synch field outside the given tolerance. lferr = lin framing error. a framing error will be flagged if dominant stop bit is sampled. same function in uart mode. ltoerr = lin time out error. a time-out error will be fl agged if the message frame is not fully completed within the maximum length t frame_maximum by any slave task upon transmission of the synch and identifier fields (see section 25.7.9 ?frame time out? on page 129 ). loverr = lin overrun error. overrun error will be flagged if a new command (other than lin abort) is entered while ?busy signal? is present. in uart mode, an overrun error will be flagged if a received byte overwrites the byte stor ed in the serial input buffer. labort lin abort transfer reflects a previous lin abort comm and (lcmd[2..0] = 000) while ?busy signal? is present. after each lin error, the lin controller stops its previous activity and returns to its wi thdrawal mode (lcmd[2..0] = 000 b ) as illustrated in figure 25-11 on page 128 . writing 1 in lerr of linsir register resets le rr bit and all the bits of the linerr register. 25.7.9 frame time out according to the lin protocol, a fr ame time-out error is flagged if: t frame > t frame_maximum . this feature is implemented in the lin/uart controller. figure 25-12.lin timing and frame time-out field field sync t he a der t he a der_nomin a l t response_nomin a l t fr a me_nomin a l = = = 34 x t bit 10 (number_of_d a t a + 1) x t bit t he a der_ nomin a l + t response_nomin a l t he a der_m a ximum t response_m a ximum t fr a me_m a ximum = = = 1.4 x t he a der_nomin a l 1.4 x t response_nomin a l t he a der_ m a ximum + t response_m a ximum t fr a me t response break field nomin a l m a ximum before time-out protected identifier field data 0 field data n checksum field 130 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.10 checksum the last field of a frame is the checksum. in lin 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and the protected id entifier. this calculation is called enhanced checksum. in lin 1.3, the checksum contains the inverted eight bit sum wit h carry over all data bytes. this calculation is called classic checksum. frame identifiers 60 (0x3c) to 61 (0x3 d) shall always use classic checksum 25.7.11 interrupts as shown in figure 25-13 on page 130 , the four communication flags of the lins ir register are combined to drive two interrupts. each of these flags have their resp ective enable interrupt bit in linenir register. (see section 25.7.7 ?xxok flags? on page 128 and section 25.7.8 ?xxerr flags? on page 129 ). figure 25-13.lin interrupt mapping checksum 255 unsigned char data n 0 n ?? ?? ?? ?? protected id. + ?? ?? ?? ?? unsigned char data n 0 n ?? ?? ?? ?? protected id. + ?? ?? ?? ?? 8 ? ?? ?? ?? ?? + ? ? ? ? ? ? ? ? ? = checksum 255 unsigned char data n 0 n ?? ?? ?? ?? unsigned char data n 0 n ?? ?? ?? ?? 8 ? ?? ?? ?? ?? + ?? ?? ?? ?? ? = labort ltoerr loverr lferr lserr lperr lcerr lberr lerr lin err lin it lidok ltxok lrxok lenerr linenir.3 linenir.2 linenir.1 linenir.0 lenidok lentxok lenrxok linsir.3 linsir.2 linerr.7 linerr.6 linerr.5 linerr.4 linerr.3 linerr.2 linerr.1 linerr.0 linsir.1 linsir.0 131 atmel ata9999 [datasheet] 8096c?avr?01/13 25.7.12 message filtering message filtering based upon the whole iden tifier is not implemented. only a status for frame headers having 0x3c, 0x3d, 0x3e and 0x3f as identifier is available in the linsir register. the lin protocol says that a me ssage with an identifier from 60 (0x3c) up to 63 (0x3f) uses a classic checksum (sum over the data bytes only). softwa re will be responsible for switchin g correctly the lin13 bit to prov ide/check this expected checksum (t he insertion of the id field in t he computation of the crc is set - or not - just after entering the rx or tx response command). 25.7.13 data management 25.7.13.1lin fifo data buffer to preserve register allocation, the lin da ta buffer is seen as a fifo (with address pointer accessible). th is fifo is accessed via the lindx[2..0] field of linsel re gister through the lindat register. lindx[2..0], the data index, is the address pointer to the requir ed data byte. the data byte can be read or written. the data index is automatically incremented after each lindat access if the lainc (active low) bit is cleared. a roll-over is implemented, after data index=7 it is data index=0. otherwise, if lainc bit is set, the data index needs to be written (updated) before each lindat access. the first byte of a lin frame is stored at the data index=0, the second one at the data index=1, and so on. nevertheless, linsel must be initializ ed by the user before use. 25.7.13.2uart data register the lindat register is the data r egister (no buffering - no fifo ). in write access, lindat will be for data out and in read access, lindat will be for data in. in uart mode the linsel register is unused. table 25-4. frame status lidst[2..0] frame status 0xx b no specific identifier 100 b 60 (0x3c) identifier 101 b 61 (0x3d) identifier 110 b 62 (0x3e) identifier 111 b 63 (0x3f) identifier 132 atmel ata9999 [datasheet] 8096c?avr?01/13 25.8 lin / uart register description 25.8.1 lincr ? lin control register bit 7 ? lswres: software reset 0 = no action, 1 = software reset (this bit is self-rese t at the end of the reset procedure). bit 6 ? lin13: lin 1.3 mode 0 = lin 2.1 (default), 1 = lin 1.3. bit 5:4 ? lconf[1:0]: configuration 1. lin mode (default = 00): 00 = lin standard configuration (listen mode ?off?, crc ?on? and frame_time_out ?on?, 01 = no crc, no time out (listen mode ?off?), 10 = no frame_time_out (listen mode ?off? and crc ?on?), 11 = listening mode (crc ?on? and frame_time_out ?on?). 2. uart mode (default = 00): 00 = 8-bit, no parity (listen mode ?off?), 01 = 8-bit, even parity (listen mode ?off?), 10 = 8-bit, odd parity (listen mode ?off?), 11 = listening mode, 8-bit, no parity. bit 3 ? lena: enable 0 = disable (both lin and uart modes), 1 = enable (both lin and uart modes). bit 2:0 ? lcmd[2:0 ]: command and mode the command is only available if lena is set. 000 = lin rx header - lin abort, 001 = lin tx header, 010 = lin rx response, 011 = lin tx response, 100 = uart rx and tx byte disable, 11x = uart rx byte enable, 1x1 = uart tx byte enable. bit 76543210 (0xc0) lswres lin13 lconf1 lconf0 lena lcmd2 lcmd1 lcmd0 lincr read/write r/w r/w r/w r/w r r/w r/w r/w initial value00000000 133 atmel ata9999 [datasheet] 8096c?avr?01/13 25.8.2 linsir ? lin status and interrupt register bits 7:5 ? lidst[2:0]: identifier status 0xx = no specific identifier, 100 = identifier 60 (0x3c), 101 = identifier 61 (0x3d), 110 = identifier 62 (0x3e), 111 = identifier 63 (0x3f). bit 4 ? lbusy: busy signal 0 = not busy, 1 = busy (receiving or transmitting). bit 3 ? lerr: error interrupt it is a logical or of linerr register bits. this bit generates an interrupt if its respective enable bit - lenerr - is set in linenir. 0 = no error, 1 = an error has occurred. the user clears this bit by writing 1 in order to reset this interrupt. resetting lerr also resets all linerr bits. in uart mode, this bit is also cleared by reading lindat. bit 2 ? lidok: iden tifier interrupt this bit generates an interrupt if its respec tive enable bit - lenidok - is set in linenir. 0 = no identifier, 1 = slave task: identifier present, master task: tx header complete. the user clears this bit by writing 1, in order to reset this interrupt. bit 1 ? ltxok: transmit performed interrupt this bit generates an interrupt if its respec tive enable bit - lentxok - is set in linenir. 0 = no tx, 1 = tx response complete. the user clears this bit by writing 1, in order to reset this interrupt. in uart mode, this bit is also cleared by writing lindat. bit 0 ? lrxok: receive performed interrupt this bit generates an interrupt if its respec tive enable bit - lenrxok - is set in linenir. 0 = no rx 1 = rx response complete. the user clears this bit by writing 1, in order to reset this interrupt. in uart mode, this bit is also cleared by reading lindat. bit 76543210 (0xc1) lidst2 lidst1 lidst0 lbusy lerr lidok ltxok lrxok linsir read/writerrrrr/w one r/w one r/w one r/w one initial value00000000 134 atmel ata9999 [datasheet] 8096c?avr?01/13 25.8.3 linenir ? lin enab le interrupt register bits 7:4 ? reserved bits these bits are reserved for future use. fo r compatibility with future devices, they must be written to zero when linenir is written. bit 3 ? lenerr: enable error interrupt 0 = error interrupt masked, 1 = error interrupt enabled. bit 2 ? lenidok: enable identifier interrupt 0 = identifier interrupt masked, 1 = identifier interrupt enabled. bit 1 ? lentxok: enable transmit performed interrupt 0 = transmit performed interrupt masked, 1 = transmit performed interrupt enabled. bit 0 ? lenrxok: enable receive performed interrupt 0 = receive performed interrupt masked, 1 = receive performed interrupt enabled. 25.8.4 linerr ? lin error register bit 7 ? labort: abort flag 0 = no warning, 1 = lin abort command occurred. this bit is cleared when lerr bit in linsir is cleared. bit 6 ? ltoerr: frame_time_out error flag 0 = no error, 1 = frame_time_out error. this bit is cleared when lerr bit in linsir is cleared. bit 5 ? loverr: ov errun error flag 0 = no error, 1 = overrun error. this bit is cleared when lerr bit in linsir is cleared. bit 4 ? lferr: framing error flag 0 = no error, 1 = framing error. this bit is cleared when lerr bit in linsir is cleared. bit 76543 2 1 0 (0xc2) ? ? ? ? lenerr lenidok lentxok lenrxok linenir read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xc3) labort ltoerr loverr lferr lserr lperr lcerr lberr linerr read/writerrrrrrrr initial value00000000 135 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 3 ? lserr: synchronization error flag 0 = no error, 1 = synchronization error. this bit is cleared when lerr bit in linsir is cleared. bit 2 ? lperr: parity error flag 0 = no error, 1 = parity error. this bit is cleared when lerr bit in linsir is cleared. bit 1 ? lcerr: checksum error flag 0 = no error, 1 = checksum error. this bit is cleared when lerr bit in linsir is cleared. bit 0 ? lberr: bit error flag 0 = no error, 1 = bit error. this bit is cleared when lerr bit in linsir is cleared. 25.8.5 linbtr ? lin bit timing register bit 7 ? ldisr: disable bit timing resynchronization 0 = bit timing re-synchronization enabled (default), 1 = bit timing re-synchronization disabled. bits 5:0 ? lbt[5:0]: lin bit timing gives the number of samples of a bit. sample-time = (1 / fclk i/o ) x (ldiv[11..0] + 1) default value: lbt[6:0]=32 ? min. value: lbt[6:0]=8 ? max. value: lbt[6:0]=63 25.8.6 linbrr ? lin baud rate register bits 15:12 ? reserved these bits are reserved for future use. for compatibility with future devices, they must be written to zero when linbrr is written. bits 11:0 ? ldiv[11:0]: scaling of clk i/o frequency the ldiv value is used to scale the entering clk i/o frequency to achieve appropriate lin or uart baud rate. bit 7654321 0 (0xc4) ldisr ? lbt5 lbt4 lbt3 lbt2 lbt1 lbt0 linbtr read/write r/w r r/(w) r/(w) r/(w) r/(w) r/(w) r/(w) initial value0010000 0 bit 76543210 (0xc5) ldiv7 ldiv6 ldiv5 ldiv4 ldiv3 ldiv2 ldiv1 ldiv0 linbrrl (0xc6) ? ? ? ? ldiv11 ldiv10 ldiv9 ldiv8 linbrrh bit 151413121110 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 136 atmel ata9999 [datasheet] 8096c?avr?01/13 25.8.7 lindlr ? lin data length register bits 7:4 ? ltxdl[3:0]: lin transmit data length in lin mode, this field gives the number of bytes to be transmitted (clamped to 8 max). in uart mode this field is unused. bits 3:0 ? lrxdl[3:0]: lin receive data length in lin mode, this field gives the number of bytes to be received (clamped to 8 max). in uart mode this field is unused. 25.8.8 linidr ? lin identifier register bits 7:6 ? lp[1:0]: parity in lin mode: lp0 = lid4 ^ lid2 ^ lid1 ^ lid0 lp1 = ! ( lid1 ^ lid3 ^ lid4 ^ lid5 ) in uart mode this field is unused. bits 5:4 ? ldl[1:0]: lin 1.3 data length in lin 1.3 mode: 00 = 2-byte response, 01 = 2-byte response, 10 = 4-byte response, 11 = 8-byte response. in uart mode this field is unused. bits 3:0 ? lid[3:0]: lin 1.3 identifier in lin 1.3 mode: 4-bit identifier. in uart mode this field is unused. bits 5:0 ? lid[5:0]: lin 2.1 identifier in lin 2.1 mode: 6-bit identifier (no length transported). in uart mode this field is unused. bit 76543210 (0xc7) ltxdl3 ltxdl2 ltxdl1 ltxdl0 lrxd l3 lrxdl2 lrxdl1 lrxdl0 lindlr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76 5 4 3210 (0xc8) lp1 lp0 lid5 / ldl1 lid4 / ldl0 lid3 lid2 lid1 lid0 linidr read/write r r r/w r/w r/w r/w r/w r/w initial value00 0 0 0000 137 atmel ata9999 [datasheet] 8096c?avr?01/13 25.8.9 linsel ? lin data buffer selection register bits 7:4 ? reserved bits these bits are reserved for future use. fo r compatibility with future devices, they mu st be written to zero when linsel is written. bit 3 ? lainc : auto increment of data buffer index in lin mode: 0 = auto incrementation of fifo data buffer index (default), 1 = no auto incrementation. in uart mode this field is unused. bits 2:0 ? lindx 2:0: fi fo lin data buffer index in lin mode: location (index) of the lin response data byte into the fifo data buffer. the fifo data buffer is accessed through lindat. in uart mode this field is unused. 25.8.10 lindat ? lin data register bits 7:0 ? ldata[7:0]: lin data in / data out in lin mode: fifo data buffer port. in uart mode: data register (no data buffer - no fifo). in write access, data out. in read access, data in. bit 76543210 (0xc9) ? ? ? ? lainc lindx2 lindx1 lindx0 linsel read/write ???? r/w r/w r/w r/w initial value ???? 0000 bit 76543210 (0xca) ldata7 ldata6 ldata5 ldata4 ldata3 ldata2 ldata1 ldata0 lindat read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 138 atmel ata9999 [datasheet] 8096c?avr?01/13 26. adc - analog to digital converter 26.1 features synchronous current and voltage adc configurable sample clock rate 512khz pll or 128khz slow rc oscillator cascaded decimation with programmable settings instantaneous measurements with programmable output rate accumulated measurements with programmable output rate programmable chopper mode to cancel offset on both current and voltage measurements programmable gain for current adc 7 selectable input channels for voltage adc diagnosis mode 26.2 overview the atmel ? avr mcu contains two separate adcs, a current a dc (c-adc) and a voltage adc (v-adc). the c-adc is dedicated to measure current flowing through an external shunt resistor. the v-adc is used to measure the battery terminal voltage, external temperature sensor or inte rnal temperature sensor. note that it also has an additional input for test intende d for self diagnosis. an overview of the adc system is illustrated in figure 26-1 on page 139 . both adcs use atmel's patented adc architecture consisting of a delta sigma modulator sampling the input, followed by 2 cascaded decimation filters which give both an instantaneous conversion result and an accumulated conversion result, trading accuracy with faster data rate. both filters have programmable decimation ratios to be able to select suitable data rates in different operation modes. decimation stage 1 outputs an instantaneous conversion result with data rate f ic . this result is typically used for monitoring rapidly changing inputs with a s horter conversion time. decimation stage 2 further accumulates th e instantaneous conversion result, giving a mean average of the input over a longer time period. the accumulated conversion will output data with a low output data rate, f ac . further accumulation of the data result should be performed in software. when both adcs are enabled, they will sample synchronously. the cpu can enable/disable eit her adc whenever it is not needed. to save power it is highly reco mmended that software dis ables the adc whenever it is not used. to ensure synchronous operation, both adcs have a common adc cont roller. the adc controller contains io registers for cpu configuration and control. by writing to the adc io registers the cpu can enable/disable the adc individually, configure the conversion ratios and chopper mode for the adcs, select input channel for the v-adc and co nfigure the gain and regular current detection mode for the c-adc. 139 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 26-1. adc overview both the c-adc and v-adc include chopper functionality to automatically cancel offs et. the chopper can be configured to run automatically or it can be controlled directly by software. wh en running in automatic settings , the chopper will automatically switch the input polarity on regular intervals and calculate a running average to remove the offset. the automatic chopping can be configured to follow the instantaneous curre nt or the accumulated conversion complete. to allow measurements on a wide range of current inputs, the c-adc has programmable gain settings. the c-adc also includes a regular current comparator. with the regular current comparator the system can be configured to enter a low power mode where it wakes up wh en current exceeds a conf igurable trigger level. the v-adc is connected to seven different sources through the input multiplexer. the pv2/nv2 pins are dedicated pins for measuring the scaled battery terminal voltage. adc0/1 are tw o general purpose inputs which ca n be configured for different external configurations. in addition to the external channels t here are two internal channels for internal temperature sensor measurement and diagnosis function. pv nv adc0 sgnd ds-mod irq decim a tion st a ge 1 w/running a ver a ge adc1 sgnd vtemp avdd/3 vref diagnosis adc0 adc1 diagnosis (pa0) (pa1) (pa1) (pa0) (pa0) (pa1) inst a nt a neous volt a ge registers accumul a ted volt a ge registers inst a nt a neous current registers accumul a ted current registers decim a tion st a ge 2 w/running a ver a ge irq ds-mod gain i n p u t m u x irq decim a tion st a ge 1 w/running a ver a ge decim a tion st a ge 2 w/running a ver a ge adc control a nd st a tus regul a r current comp a r a tor irq irq pi ni 140 atmel ata9999 [datasheet] 8096c?avr?01/13 26.3 operation 26.3.1 delta sigma modulator the delta sigma modulator will perform oversampling and quanti zation of the input signal and do noise shaping of the quantization error. the input for both the c-adc and the v-adc will be sampled at ei ther the 512khz pll clock or the 128khz slow rc oscillator, depending on cksel io bit in section 26.6.3 ?adcra - adc control register a? on page 151 . to avoid aliasing when sampling the input, the input needs to be band limited by an external filt er. due to the high oversampli ng of the delta sigma modulator a first orde r passive rc filter should be sufficient. the adcs use the vref as reference voltage. for details on this voltage see section 27. ?band gap reference and temperature sensor? on page 161 . the voltage reference, vref, is used to cr eate the internal quantization range for the delta sigma modulator. the v-adc uses single ended sampling, and the in ternal quantization range is from gnd to fsr ,v-adc . the v-adc has no internal gain for the external channels and will quantiz e the input relative to the full-scale range, fsr ,v-adc . the c-adc uses differential signaling to be able to measure bo th charge and discharge currents. the internal signal range of the current adc is -?fsr ,c-adc to ?fsr ,c-adc . the current adc has programmable gain and the input range depends on the gain settings. for details on gain settings, see section 26.3.3 ?programmable gain? on page 141 . the figure below illustrates the fsr of the v-adc and the c-adc figure 26-2. internal signal range with vref = 1.1v to ensure stable modulator operation, the input voltage/current should be limited to 90% of the modulator full scale range (fsr). note that if the input voltage exceeds the allowable input range (f sr), the conversion register will saturate. the conversion w ill then give max or min values in the data registers. 26.3.2 programmable de cimation filters the output of the delta sigma modulator contains a noise shaped, oversampled signa l representing the input signal together with both in and out-of band co mponents. in order to remove the out-of band noise, the digital adc contains 2 cascaded decimation filters which will band limit the input with a low-pass filter before down-s ampling the signal. the output of both f ilters can be read by the software. figure 26-3. decimation filter 2 n qu a ntiz a tion levels fsr, v-adc = 1.1v gnd 2 n qu a ntiz a tion levels ? fsr, c-adc = 0.66v - ? fsr, c-adc = 0.66v digit a l low p a ss filter d1 adides [1:0] adades [2:0] inst a nt a neous conversion accumul a ted conversion decim a tion filter st a ge 1 f ic f s f ac digit a l low p a ss filter d2 decim a tion filter st a ge 1 141 atmel ata9999 [datasheet] 8096c?avr?01/13 each filter has programmable decimation fact ors that can be adjusted by writing to the adides[1:0] and adades[2:0] io bits in section 26.6.5 ?adcrc - adc control register c? on page 153 . figure 26-3 shows the decimation filter and their conversion outputs. the first decimation filt er will output an instantaneous data conversion every 512, 256, 128 or 64 sampling cycle. the second decimation filter will output an accumulated conversion result every 512, 256, 128, 64, 32, 16, 8 or 4th instantaneous conversion. the data output rate f ic and f ac for the instantaneous and accumulated co nversion output as a function of the decimation settings is given in the equation below. note that when either automatic fast or slow chopping is enabled the data rate will be lower. for details on data rates when chopping is enabled, see section 26.3.4 ?programmable c hopper control? on page 142 . 26.3.3 programmable gain the c-adc has programmable input gain settings to be able to me asure a wide range of current inputs. when a small current is flowing the input can be scaled to fit the operation range of the adc. the input gain will adjust the signal at the input before it is sampled and quantized by the delta sigma modulator. the input g ain has 7 programmable gain levels which can be selected by softwa re by writing to the cadg2:0 bits. 4x, 8x, 16x, 32x, 64x, 128x or 256x can be selected. figure 26-4. analog gain stage at input note that the gain stage will saturate if the input exceeds the range of the modulator. the data result will then give max posi tive or min negative values in the data registers. f ic f s 64 2 adides[1:0] ------------------------------------------- = f ac f ic 2 adiades[2:0] 2 + ---------------------------------------- - = gain cadg [2:0] pi vin+ vin- ni ds-mod ? fsr, c-adc - ? fsr, c-adc 142 atmel ata9999 [datasheet] 8096c?avr?01/13 26.3.4 programmable chopper control both the c-adc and v-adc have a chopper f eature to cancel offset in the conversi on data. the chopper can be configured by writing to the adcms1:0 io bits in the section 26.6.3 ?adcra - adc c ontrol register a? on page 151 . if enabled, the chopper can be configured to run with in either automatic fast chopper mode automatic slow chopper mode software polarity control mode figure 26-5 gives an overview of the chopper functionality. figure 26-5. chopper overview if selecting the automatic fast chopper mode the chopper will switch the polarity of the input on each instantaneous conversion and calculate running averaging on the last two conv ersion results. in automatic fast chopper mode the adc will automatically perform two sett ling conversions before using the 3rd instant aneous conversion for running average, hence the instantaneous conversion data rate is re duced by 3x compared to having the fast chopper off. to get accurate accumulation conversion result the settling conversions in the instantaneous filter ar e not used by the second decimation filter stage; henc e the data rate in the accumulated conversion is also redu ced by 3. the fast chopper timing is illustrated in figure 26-6 . figure 26-6. fast chopper timing inst a nt a neous current registers accumul a ted current registers ds-mod decim a tion st a ge 1 0 1 decim a tion filter running aver a ge adcms = autom a tic f a st chopper mode adcms = autom a tic slow chopper mode pi ni decim a tion st a ge 2 0 1 decim a tion filter running aver a ge cadcms 1:0 01 settling settling settling d a t a 1 (no chopper) d a t a 3 ( a ver a ging) chopper pol a rity inst a nt a neous conversion inst a nt a neous conversion complete 143 atmel ata9999 [datasheet] 8096c?avr?01/13 if selecting automatic slow chopper mode the chopper will s witch polarity on each accumulated conversion and calculate running average on the last two conversion results. note that when the chopper switches the polarity the instantaneous filter w ill need 2 settling samples, these settling samples are automatically discarded at the input of the accumulation filter reducing th e data rate of the accumulated conversion with the time it take s to convert two instantaneous conversion values. the extra conversion delay is illustrated in figure 26-7 . figure 26-7. slow chopper timing if selecting software polarity co ntrol mode, the cpu can se lect the chopper po larity by writing to the adpsel bit. in this mode software could change the polarity on regular intervals and do settling and running average in software. note that the adpsel bit will be synchronized together with other control settings to the adc. for details on synchronization, see section 26.4.1 ?synchronization of configuration settings? on page 146 . when enabling automatic chopper mode, the first result will take twice as long since an running average value has to be calculated. this is also the case when changing between automatic fast and slow chopper mode. table 26-1. data rates for instantaneous (ic) and accumulated (ac) conversion (1)(3) chopper mode f ic f ac auto fast chopper auto slow chopper (2) no chopper notes: 1. output sampling rate as function of decimation settings and input sampling rate, f s . 2. settling of instantaneous is handled in hardware. after the chopper polarity is swit ched, 2 cadic result is auto- matically discarded. 3. icdec represents the configured ic decimation ratio. acdec represents the configured ac decimation ratio. cadcms [1:0] 10 d2 (ades 1:0) ic s a mples used by accumul a tion filter 2 ic settling s a mples disc a rded by accumul a tion filter chopper pol a rity accumul a ted conversion accumul a ted conversion irq inst a nt a neous conversion irq f s 3 icdec ? ----------------------------- f s 3 icdec acdec ?? --------------------------------------------------------- - f s icdec ------------------ - f s 2 icdec ? () icdec acdec ? () + --------------------------------------------------------------------------------------------- f s icdec ------------------ - f s icdec acdec ? ----------------------------------------------- 144 atmel ata9999 [datasheet] 8096c?avr?01/13 26.3.5 programmable regulator current comparator to be able to minimize cpu workload, the c-adc can be c onfigured to run with the regular current comparator enabled. enabling this feature allows the cpu to wake up only when the current is higher than a programmable threshold for a programmable number of samples. figure 26-8. regulator current comparator by writing to the section 26.6.5 ?adcrc - adc control register c? on page 153 , regular current comparator can either be enabled or disabled, and the regular current counter mode of operation and timeout can be selected. the value of the comparator threshold can be c onfigured by writing to the section 26.6.10 ?cadrclh and cadrcll - c-adc regulator current comparator threshold level? on page 157 . if enabled, the regular current com parator will increment the regular current counter when the absolut e value of the accumulated cu rrent measurement exceeds the programmable threshold level. if the accumulated current meas urement goes below the threshol d, the counter will either rese t or decrement depending on the configuration. when the counter reaches the configured timeout level, the regular current comparator can be configured to give a regular current detection interrupt to the cpu. figure 26-9 illustrates the regular current comparator timing wit h the counter configured to reset when going below the threshold level. figure 26-9. regulator current timing with counter reset cadrcm [1:0] cadac [31:16] regul a r current comp a re rc counter irq regul a r current comp a r a tor cadrcl [15:0] cadrct [3:0] 00 12 no w a keup condition w a keup condition current 34567 cadrcen = 0x1 cadrct = 0xc 123456789abc regul a r current irq comp a r a tor threshold regul a r current count accumul a ted current complete 145 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 26-10 illustrates the regular current compar ator timing with the counter configured to decrement when going below the threshold level. figure 26-10.regulator current timing with counter decrement when the regular current comparator has detected a regular current condition this will automatically reset the regular current counter. the regular current counter will also reset if software changes configuration from reset to decrement or decrement to reset mode. if the cadac conversion result is bl ocked by a read out busy, the regular current comparator will not be affected. 26.3.6 conversion result for the c-adc the current flowing through the ex ternal shunt is given by the following equation. for the v-adc the following equations is us ed to calculate the external voltage. in both expressions n is the number of data bits in the c onversion word. the instantaneous conversion result has 16 bits resolution for both the c-adc and the v-adc while the accumulate d conversion has 18 bits for the c-adc and 17 bits for the v-adc. 012 w a keup condition current 34567 cadrcen = 0x2 cadrct = 0xc 65456789 b ac regul a r current irq comp a r a tor threshold regul a r current count accumul a ted current complete current |fsr| r shunt 2 n-1 input gain ----------------------------------------------------------------- conversion word = voltage fsr 2 n ---------- conversion word = 146 atmel ata9999 [datasheet] 8096c?avr?01/13 26.4 configuration and usage 26.4.1 synchronization of configuration settings the adcs operate in a different clock domain than the cpu. fo r safe synchronization and seamless configuration changes the v-adc and c-adc have a common configuration controller. when th e cpu writes new configuration data to the adc, the data are placed in temporary buffers. when all configuration changes have been written to th e io registers, the scmd1:0 bits should be written to execute the synchronization command. this will st art the synchronization of data to the adc domain. depending on command written the adc will either: update to new settings immediately wait for the next instantaneous conversion before updating to new settings wait for the next accumulated conversion before updating to new settings while new configuration changes are being synchronized, the temporary buffers are lo cked for further writing until the data hav e been synchronized to the adc domain. during synchro nization, the sbsy bi t will stay high until synchro nization is completed. the cpu can therefore monitor the status of the synchronization by reading this bit. the cpu/adc synchronizati on is illustrated in figure 26-11 . figure 26-11.synchronization of configuration settings to ensure safe configuration changes, the following sequence should be used: 1. check that the sbsy is low 2. write new configuration settings (adcsr, adcra, adcrb, adcrc, ?) 3. write scmd1:0 to the preferred setting. if both adcs are disabled, they can be c onfigured immediately without waiting for an instantaneous or accumulated conversion complete. in this case, the synchronization will take place immedi ately regardless of what is written to the scmd1:0 bits. note however that due to synchronization between the different clo ck domains, 2-3 adc clock cycles are required befor e the actual configuration takes place. if doing an immediate update to new settings, the adc wi ll automatically reset before applying the new settings. when software does a configuration change by sending a synchro nization command that should do reconfiguration at either next instantaneous or accumulated conversi on edge, the synchronization command regi ster scmd1:0 has to be written with a time margin to the next instantaneous or accumulated conver sion edge. to guarantee that the reconfiguration is done at the following edge, so ftware has to write the co mmand at least 35 adc clo ck cycles before the next conv ersion edge is expected. it software writes the co mmand too late, the reconfig uration will not be updated unt il the next conversion edge. depending on usage and the conversion result used by softw are, different synchronization methods are recommended: when either accumulated conversion result or both th e instantaneous and the accumulated conversions are used by software, it is recommended to always synchronize confi guration changes on the next accu mulated conversion edge or immediately. when only the instantaneous conversion result is used by software, it is recommended to always synchronize configuration changes on the next accumu lated conversion edge or immediately. when software enters or exit software polarity control m ode it is recommended to synchronize configuration changes immediately. adc configur a tion (cpu buffer) adc configur a tion control adc configur a tion (adc dom a in) c-adc data b u s synchroniz a tion comm a nds synchronize d a t a synchroniz a tion st a tus v-adc 147 atmel ata9999 [datasheet] 8096c?avr?01/13 26.4.2 initialization and settling time when the adcs are enabled (both disabled in advance) an extra init ialization time of 30-40 adc cycles is required until the fir st conversion is ready. the same initialization time is require d when software executes an immediate configuration change command. when applying new changes the adc will need to do settling conv ersions before an actual conversion is ready. if using automatic fast/slow chopper mode, the settli ng will automatically be handled in hardware, in other cases the settling must be handled by the software. if not using automatic fast/slow chopper mode, settling should be handled in user software by discarding the first two instantaneous conversions and the first accumulation conversi on result after doing a configuration change that requires settling. for both adcs, settling is required when enabling the adc, af ter changing the decimation rati os, after changing the polarity of the chopper, after changing the sampling clock source an d after leaving automatic chopper mode configuration. for the c-adc, settling time is required when changing the input gain settings. for the v-adc, settling ti me is required when changing conversion channel. the settling time is summarized in table 26-2 . 26.4.3 sampling clock software can select either the 512khz pll clock or the 128khz slow rc oscillator as sampling clock for the adc by writing to the cksel bit in section 26.6.3 ?adcra - adc control register a? on page 151 . when changing clock configuration this will be synchronized in the same way as other configuration settings. note that if the pll has been selected as adc clock the pll will keep running even if the cpu has entered sleep modes where the pll should be automatically disabled. whenever going to dee p sleep modes it is recommended to always use the slow rc oscillator as sampling clock. this allows the pll to be au tomatically switched off which gi ves minimum power consumption. if changing to the pll clock source software should make sure that the pll has locked to the target frequency before using the conversion data. when changing sampling clock on the next conversion, the clo ck change will take affect about 35 adc clock cycles before the corresponding interrupt is set. note therefore that the conversion time of the ongoing conversions will be affected. table 26-2. s ettling time for the in s tantaneo us (ic) and acc u m u lated (ac) conver s ion chopper mode t settling,ic t settling,ac auto fast chopper (1) auto slow chopper (2) no chopper (3) notes: 1. the first accumulated conversi on must be discarded in software. 2. the instantaneous conversion offset removal has to be performed in software. 3. settling should be performed in software when app lying configuration changes that require settling. 4. whenever doing configuration cha nges the recommended synchronization methods should be used. other- wise one extra settling conversion has to be added. for details on synchronization, see section 26.4.1 ?synchronization of configuration settings? on page 146 . 2 f ic ------- - 2 f ac --------- - 2 f ic ------- - 2 f ac --------- - 2 f ic ------- - 2 f ac --------- - 148 atmel ata9999 [datasheet] 8096c?avr?01/13 26.4.4 interrupts the two adcs have five interrupt sources. each inte rrupt source can be disabled individually. the interrupts are shown in the figure below. figure 26-12.adc interrupts both the v-adc and the c-adc can be config ured to issue an interrupt on each instantaneous and accumulated conversion. in addition the c-adc can be configured to issue an in terrupt when a regular current detection occurs. when the c-adc is configured to run in with the regular cu rrent comparator enabled, the instantaneous and accumulated conversion complete interrupts are still available. to avoid waki ng up whenever there is no regular current condition, the c- adc should have only the regular current detection interrupt enabled in this mode. 26.4.5 configuring adc1 and adc0 for v-adc operation when one of the adc0 or adc1 is used as analog input to the v-adc, either adc0 or adc1 can be used as signal ground (sgnd). the use of adc1 and adc0 as sgnd is effi cient for the thermistor configuration shown in figure 26-13 . both thermistors, are connected through a comm on divider resistor to adc0 and adc1 respectively. both adc0 and adc1 have very high input impedance when used as adc inputs, which makes it possible to connect two thermistors in the configuration shown in figure 26-13 . when measuring the adc0/adc1 channel in this configur ation the adc1/adc0 is automatically switched to sgnd. figure 26-13.thermistor configuration in addition to the thermistor configuration in figure 26-13 , adc0/adc1 can also be configured to measure the pin voltage without using the sg nd configuration. it is recommended to set the pa0did and pa1did bits to avoid high current consumption on the digital input buffer. when measuring at adc0, software should configure adc0 as an input. when measuring at adc1, software should configure adc1 as an input. c-adc cadicif cadic irq cadac irq cadrc irq cadicie cadacif cadacie cadrcif cadrcie v-adc vadicif vadic irq vadac irq vadicie vadacif vadacie vref adc1/sgnd adc0/sgnd vrefgnd 149 atmel ata9999 [datasheet] 8096c?avr?01/13 26.4.6 configuration changes and sleep mode to ensure the lowest power consumption in power-down, it is recommended to disable both the cadc and the vadc by clearing the caden and vaden bits before entering sleep. when configuring the adc, the actual conf iguration will not be completed until synchronization has been completed. to ensure correct operation it is not recommended to enter sleep unti l the synchronization has been completed and the sbsy bit in section 26.6.1 ?adscsra - adc synchronization control and status register a? on page 149 is cleared 26.5 diagnosis mode both the v-adc and the c-adc features diagnosis capability. the v-adc has a separate diagnosis input chan nel to check that the voltage reference is within its range. the voltage on this channel is vref/2. when this channel is selected avdd/3 should be selected as reference voltage. in addition the v-adc has pull-up functionality on the pv2 and nv2 pins that can be enabled to check for opens and shorts on these pins. the pull-up is enabled by configuring the vadpdm[1:0] bits in adcre. plea se note that this pull-up resistor is connected to vref. the c-adc has a diagnosis input channe l with a fixed input voltage of 3/40 vref that can be used to check the c-adc. in addition it feature pull-up functionality on the pi and ni pins that can be enabled to check for opens on these pins. the pull- up is enabled by configuring the cadpdm[1:0] bits in adcrd. please note that this pull-up resi stor is connected to vref. 26.6 register description 26.6.1 adscsra - adc synchronization control and status register a bit 7:3 - reserved these bits are reserved and will always read as zero. bit 2 - sbsy: synchronization busy this bit shows the status of the synchronization command fr om the cpu to the adc domain. when this bit is set syn- chronization is busy, and the configurat ion changes are pending. when this bit is cleared synchronization is ready and the adc is ready to be reconfigured. when the sbsy is high software writing to the following adc registers are blocked by hardware; adscsr, adcra, adcrb, adcrc, adcrd, adcre and cadrclh and cardrll. bit 1:0 - scmd[1:0]: sy nchronization command by writing to these bits a synchronization command is is sued from the cpu domain to the adc domain. the adc will update the new settings based on the synchronization command. table 26-3 shows the synchronization commands from the cpu to the adc. when writing to these bits while the sbsy bit is low, a synchronization command is issued and sbsy will go high. any writing to these bits while the sbsy bit is high will be ignored. when sbsy is high the ongoing command will be present in the scmd1:0 bits. when sbsy goes low the scmd1:0 bits are aut omatically cleared. bit 7 6 5 4 3 2 1 0 (0xe0) ? ? ? ? ? sbsy scmd1 scmd0 adscsra read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-3. cpu s ynchronization command s scmd[1:0] synchronization command 00 no synchronization 01 reset and synchronize 10 synchronize on next instantaneous conversion 11 synchronize on next accumulated conversion 150 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.2 adscsrb - adc synchronization control and status register b bit 7 - reserved this bit is reserved and will always read as zero. bit 6 - vadicps: v-adc instantaneous conversion polarity status when the automatic chopper is configured to run in automatic slow chopping mode, this bit shows the polarity of the conversion present in the v-adc inst antaneous conversion registers, vadicl and vadich. this bit should be read before reading out the instantaneo us conversion result to ensure correct pola rity information. in other modes this bit will always read as zero. for details on chopping, see section 26.3.4 ?programmable chopper control? on page 142 . bit 5 - vadacrb: vadac data read out busy this bit will be set when reading either the vadac0, vadac 1 or vadac2 data registers and cleared when reading the vadac3 data register. when the vadacrb bit is set it means that a data read out is busy and during this time v-adc accumulated conversion registers are blocked for further up date. if a read out is busy when a new v-adc accumulated conversion value is ready, both the new conversion value and setting of the interrupt flag will be lost. bit 4 - vadicrb: vadic data busy read this bit will be set when reading the vadicl data register and cleared when reading the vadich data register. when the vadicrb bit is set it means that a data read out is bu sy and during this time v-adc in stantaneous voltage registers are blocked for further update. if a read out is busy when a new v-adc instantaneous conversion value is ready, both the new conversion value and setting of the interrupt flag will be lost. bit 3 - reserved this bit is reserved bits and will always read as zero. bit 2 - cadicps: c-adc instantane ous conversion polarity status when the automatic chopper is configured to run in automatic slow chopping mode, this bit shows the polarity of the conversion present in the c-adc instan taneous conversion registers, cadicl and cadich. this bit should be read before reading out the instantaneo us conversion result to ensure correct pola rity information. in other modes this bit will always read as zero. for details on chopping, see section 26.3.4 ?programmable chopper control? on page 142 . bit 1 - cadacrb: cadac data read out busy this bit will be set when reading either the cadac0, cadac1 or cadac2 data registers an d cleared when reading the cadac3 data register. when the cadacrb bit is set it means that a data read out is busy and during this time c-adc accumulate conversion registers are bloc ked for further update. if a read out is busy when a new c-adc accumulated conversion value is ready, both the new conversion value and setting of the interrupt flag will be lost. bit 0 - cadicrb: cadic data read out busy this bit will be set when reading the cadicl data register and cleared when reading the cadich data register. when the cadicrb bit is set it means that a data read out is busy and during this ti me c-adc instantaneous conversion regis- ters are blocked for further update. if a read out is busy when a new c-adc instantaneous current value is ready, both the new conversion value and setting of the interrupt flag will be lost. bit 76 5 432 1 0 (0xe1) ? vadicps vadacrb vadicrb ? cadicps cadacrb cadicrb adscsrb read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 151 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.3 adcra - adc control register a bit 7:4 - reserved theser bits are reserved and will always read as zero. bit 4 - adpsel: adc polarity select this bit is used to control the polarity when running softwa re polarity control operation. to write this bit to '1', the adcms1:0 bits have to be written to '11' at the same time, otherwise this bit will not be set. bit 2:1 - adcms[1:0]: c-adc chopper mode select these bits are used to configure the chopper for the adcs according to table 26-4 . bit 0 - cksel: sampling clock select this bit selects the sampling clock for both adcs. by writing this bit to one the slow rc oscillator will be used as sampling clock. table 26-5 shows the sampling clock selection for the adc. note that to avoid getting wrong data re sult by changing the clock in the middle of a conversion, adc clock changing is synchronized along with other configuration changes. bit 7 6 5 4 3 2 1 0 (0xe2) ? ? ? ? adpsel adcms[1:0] cksel adcra read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-4. chopper mode selection adcms[1:0] chopper mode select 00 chopping disabled 01 automatic fast chopping 10 automatic slow chopping 11 software polarity control table 26-5. sampling clock selection cksel adc clock source 0 pll (512khz output) as sampling clock 1 slow rc oscillator as sampling clock 152 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.4 adcrb - adc co ntrol register b bit 7:5 - reserved theser bits are reserved and will always read as zero. bit 4:3 - adides[1:0]: instanta neous decimation ratio select these bits determine the decimation ratio for the instantane ous conversion output. the same settings apply for both the c-adc and the v-adc. bit 2:0 - adades[2:0]: accumulated decimation ratio select these bits determine the decimation ratio for the accumulate d conversion output. the same settings apply for both the c-adc and the v-adc. bit 7 6 5 4 3 2 1 0 (0xe3) ? ? adides[1:0] adades[2:0] adcrb read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-6. instantaneous decimation ratios adides[1:0] instantaneous decimation ratio 00 512 01 256 10 128 11 64 table 26-7. accumulated decimation ratios adades[2:0] accumulated deci mation ratio 000 512 001 256 010 128 011 64 100 32 101 16 110 8 111 4 153 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.5 adcrc - adc control register c bit 7 - caden: c-adc enable this bit is used to enable the c-adc. when this bit is se t to one the c-adc will be enabled. when clearing this bit the c- adc will be disabled. bit 6 - reserved this bit is reserved and will always read as zero. bit 5:4 - cadrcm[1:0]: c-adc regu lar current comparator mode these bits are used to enable the regular current comp arator and to configure t he regular current counter. bit 7-4 - cadrct[3:0]: c-adc regu lar current count threshold these bits determine number of accumula ted current measurements that must be above the regular current threshold level before a regular current condition occurs. bit 76543210 (0xe4) caden ? cadrcm[1:0] cadrct[3:0] adcrc read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-8. regular current comparator mode cadrcm[1:0] regular current comparator mode 00 comparator disabled 01 comparator enabled. the regular current counter counts up if accu mulated current measurement is above threshold and it is reset if the accumulated current goes below threshold. 10 comparator enabled. the regular current counter counts up if accu mulated current measurement is above threshold and down towards 0 if accumulated current goes below threshold. 11 reserved table 26-9. regular current count threshold cadrct[3:0] number of sample above threshold 0000 1 0001 2 0010 3 ... ... 1111 16 154 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.6 adcrd - adc co ntrol register d bits 7:6 - reserved these bits are reserved and will always read as zero. bit 5:3 - cadg[2:0]: c-adc gain these bits determine the gain in the analog input stage of the c-adc according to table 26-10 . bit 2:1 - cadpdm[1:0]: c- adc pin diagnostics mode these bits are used to enable diagnosis pull-up voltages for hence the pi and ni input pins of the c-adc according to table 26-11 . bit 0 - caddsel: c-adc diagnosis channel select when this bit is set, the c-adc will select a diagnosis vo ltage input corresponding to 3/40vref. when using this chan- nel the c-adc gain, cadg[1:0] bits, shoul d be configured with 4x setting. when this bit is cleared the pi and ni will be used as inputs for the c-adc. bit 7 6 54321 0 (0xe5) ? ? cadg[2:0] cadpdm[1:0] caddsel adcrd read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-10. input gain cadg[2:0] input gain 000 4x 001 8x 010 16x 011 32x 100 64x 101 128x 110 256x 111 reserved table 26-11. pin diagnosis mode cadpdm[1:0] description 00 pull-up disabled 01 pull-up on pi pin enabled 10 pull-up on ni pin enabled 11 pull-up on both pi/ni pins enabled 155 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.7 adcre - adc control register e bit 7 - vaden: v-adc enable this bit is used to enable the v-adc. when this bit is se t to one the v-adc will be enabled. when clearing this bit the v- adc will be disabled . bit 6 - reserved this bit is reserved and is always read as zero. bit 5 - vadrefs: v-adc reference select this bit is used to select the reference voltage for the v-adc according to table 26-12 . bit 4:3 - vadpdm[1:0]: v-adc pin diagnostics mode these bits are used to enable diagnosis pull-up voltages for he nce the pv2 and nv2 input pins of the v-adc according to table 26-13 . bit 2:0 - vamux[2:0]: v-adc channel selection bits this vamux bits determine the v-adc channel selection according to table 26-14 . bit 7 6 5 4 3 2 1 0 (0xe6) vaden ? vadrefs vadpdm[1:0] vamux[2:0] adcre read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 26-12. v-adc reference select vadrefs description 0 vref as reference 1 avdd/3 as reference (for diagnosis purpose) table 26-13. pin diagnosis mode vadpdm[1:0] description 00 pull-up disabled 01 pull-up on pv2 pin enabled 10 pull-up on nv2 pin enabled 11 pull-up on both pv2/nv2 pins enabled table 26-14. v-adc channel selection vamux[2:0] channel selected 000 pv2 - nv2 001 adc0 - sgnd (1) 010 adc1 - sgnd (2) 011 vtemp - gnd 100 diagnosis (vref/2) - gnd 101 adc0 - gnd 110 adc1 - gnd 111 reserved notes: 1. adc1 will automatically be configured as sgnd. 2. adc0 will automatically be configured as sgnd. 156 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.8 adifr - adc inte rrupt flag register bits 7:6 - reserved these bits are reserved and will always read as zero. bit 5 - vadacif: accumulated conversion interrupt flag this bit is set when the v-adc completes an accumulated conversion and the v-adc accumulated conversion regis- ters are updated. the v-adc accumulated conversion complete in terrupt is executed if the vadacie bit and the i-bit in sreg is set. vadacif is cleared by hardware when executi ng the corresponding interrupt handling vector. alternatively, vadacif is cleared by writing a logical one to the flag. be ware that if doing a read-mod ify-write on adifr, a pending interrupt can be lost. bit 4 - vadicif: instantaneous conversion interrupt flag this bit is set when the v-adc completes an instantaneous conversion and the v-adc instantaneous conversion regis- ters are updated. the v-adc instantaneous conversion complete interrupt is executed if the vadicie bit and the i-bit in sreg is set. vadicif is cleared by hardware when execut ing the corresponding interrupt han dling vector. alternatively, vadicif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adifr, a pending interrupt can be lost. bit 3 - reserved this bit is reserved and will always read as zero. bit 2 - cadrcif: regulator current interrupt flag this bit is set when a c-adc has detected that a regular current condition has occurred. the c-adc regular current interrupt is executed if the cadrcie bit and the i-bit in sr eg is set. cadrcif is cleared by hardware when executing the corresponding interrupt handling vect or. alternatively, cadrcif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adifr, a pending interrupt can be lost. bit 1 - cadacif: accumulated conversion interrupt flag this bit is set when the c-adc completes an accumulat ed conversion and the c-adc accumulated conversion regis- ters are updated. the c-adc accumulated conversion complete interrupt is executed if the cadacie bit and the i-bit in sreg is set. cadacif is cleared by hardware when exec uting the corresponding interrupt handling vector. alterna- tively, cadacif is cleared by writing a logical one to the fl ag. beware that if doing a read-modify-write on adifr, a pending interrupt can be lost. bit 0 - cadicif: instantaneous conversion interrupt flag this bit is set when a c-adc completes an instantaneous co nversion and the c-adc instantaneous conversion regis- ters are updated. the c-adc instantaneous conversion complete interrupt is executed if the cadicie bit and the i-bit in sreg is set. cadicif is cleared by ha rdware when executing the corresponding interrupt handling vector. alternatively, cadicif is cleared by writing a logical one to the flag. be ware that if doing a read-modify-write on adifr, a pending interrupt can be lost. bit 7 6 5 4 3 2 1 0 (0xe7) ? ? vadacif vadicif ? cadrcif cadacif cadicif adier read/write r r r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 157 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.9 adimr - adc interrupt mask register bit 7:6 - reserved these bits are reserved and will always read as zero. bit 5 - vadacie: accumulated conversion interrupt enable when this bit is written to one and the i-bit in sreg is se t, the v-adc accumulate conversion complete interrupt is activated. bit 4 - vadicie: instantaneous conversion interrupt enable when this bit is written to one and the i-bit in sreg is se t, the v-adc instantaneous conver sion complete interrupt is activated. bit 3 - reserved this bit is reserved and will always read as zero. bit 2 - cadrcie: regular current interrupt enable when this bit is written to one and the i-bit in sreg is set, the c-adc regular current detection interrupt is activated. bit 1 - cadacie: accumulated conversion interrupt enable when this bit is written to one and the i-bit in sreg is se t, the c-adc accumulated conversion complete interrupt is activated. bit 0 - cadicie: instantaneous conversion interrupt enable when this bit is written to one and the i-bit in sreg is set, the c-adc instantaneous conver sion complete interrupt is activated. 26.6.10 cadrclh and cadrcll - c-adc regula tor current comparator threshold level bit 15:0 - cadrcl[15:0]: c-adc regulator current threshold level the c-adc regular current comparator threshold regist ers, cadrclh and cadrcll determine the threshold level for the regular current comparator det ection. the value is in unsigned format and bit 15 will always read zero. bit 7 6 5 4 3 2 1 0 (0xe8) ? ? vadacie vadicie ? cadrcie cadacie cadicie adimr read/write r r r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 (0xea) cadrcl[15:8] cadrclh (0xe9) cadrcl[7:0] cadrcll 76 5 4 3 2 1 0 read/write r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 158 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.11 vadich and vadicl - v-adc instantaneous conversion result when a v-adc instantaneous conversion is complete, the result is found in these two regi sters. the vadich and vadicl contain the instantaneous voltage measurements in unsigned format. when vadicl is read, the v-adc instantaneous conversion register is not updated unti l vadich is read. during a read of the data values the vadic read out busy flag, vadicrb in section 26.6.2 ?adscsrb - adc sy nchronization control and status register b? on page 150 will be high. reading the registers in the sequence vad icl, vadich will ensure that consistent values are read. when a conversion is completed, both registers must be read before the nex t conversion is completed, otherwise data will be lost. 26.6.12 vadac3, vadac2, vadac1 and vadac0 - v-adc accumulate d conversion result when a v-adc accumulated conversion is complete, the result is found in these four re gisters. the vadac3, vadac2, vadac1 and vadac0 registers contain the accumulate voltage measurements in unsigned format. bits 31:15 are the 17-bit adc result, while bits 14:0 will read all zeros. when vadac0, vadac1 or vadac2 is read, the v-adc accumu lated conversion register is not updated until vadac3 is read. during a read of the data values the vadac read out busy flag, vadacrb in adscsrb - adc synchronization control and status register b will be high. reading the re gisters in the sequence vadac0, vadac1, vadac2, vadac3 will ensure that consistent values are read. w hen a conversion is completed, all registers must be read before the next conversion is completed, otherwise data will be lost. bit 15 14 13 12 11 10 9 8 (0xf2) vadich[15:8] vadich (0xf1) vadicl[7:0] vadicl 76 5 4 3 2 1 0 read/write r r r r r r r r rr r r r r r r initial value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 (0xf6) vadac3[31:24] vadac3 (0xf5) vadac2[23:16] vadac2 (0xf4) vadac1[15:8] vadac1 (0xf3) vadac0[7:0] vadac0 read/write r r r r r r r r rr r r r r r r rr r r r r r r rr r r r r r r initial value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 159 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.13 cadich and cadicl - c-adc instantaneous conversion result when a c-adc instantaneous conversion is complete, the result is found in these two registers. the cadich and cadicl contain the instantaneous current measurem ents in 2's complement format. when cadi cl is read, the c-adc instantaneous conversion register is not updated until ca dich is read. during a read of the data values the cadic read out busy flag, cadicrb in section 26.6.2 ?adscsrb - adc synchronization control and status register b? on page 150 will be high. reading the registers in the sequence cadicl, cadich will ensu re that consistent values are read. when a conversion is completed, both registers must be read before the next conversion is completed, otherwise data will be lost. 26.6.14 cadac3, cadac2, cadac1 and cadac0 - c-adc accumulated conversion result when a c-adc accumulated conversion is complete, the result is found in these four registers. the cadac3, cadac2, cadac1 and cadac0 registers contain the accumulate current measurements in 2's complement format. bits 31:14 are the 18-bit adc result (including sign), while bit 13:0 will read a ll zeros for positive results and all ones for negative results. when cadac0, cadac1 or cadac2 is read, the c-adc accumulated conversion regi ster is not updated until cadac3 is read. during a read of the data values t he cadac read out busy flag, cadacrb in section 26.6.2 ?adscsrb - adc synchronization control and st atus register b? on page 150 will be high. reading the regi sters in the sequence cadac0, cadac1, cadac2, cadac3 will ensure that consistent values are read. when a conver sion is completed, all registers must be read before the next conversion is completed, otherwise data will be lost. bit 15 14 13 12 11 10 9 8 (0xec) cadich[15:8] cadich (0xeb) cadicl[7:0] cadicl 76 5 4 3 2 1 0 read/write r r r r r r r r rr r r r r r r initial value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 (0xf0) cadac3[31:24] cadac3 (0xef) cadac2[23:16] cadac2 (0xee) cadac1[15:8] cadac1 (0xed) cadac0[7:0] cadac0 read/write r r r r r r r r rr r r r r r r rr r r r r r r rr r r r r r r initial value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 160 atmel ata9999 [datasheet] 8096c?avr?01/13 26.6.15 didr0 ? digital in put disable register 0 bit 7:2 - reserved these bits are reserved and is always read as zero. bit 1:0 - pa1did:pa0did when this bit is written logic one, the digital input bu ffer on the corresponding adc pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the pa1did:pa0did pin and the digital input from this pin is not needed, this bi t should be written logic one to reduce power consumption in the digital input buffer. bit 7 6 5 4 3 2 1 0 (0x7e) ? ? ? ? ? ? pa1did pa0did didr0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 161 atmel ata9999 [datasheet] 8096c?avr?01/13 27. band gap reference and temperature sensor 27.1 features accurate voltage reference of 1.100v internal temperature sensor curvature compensation to cancel higher order temperature dependence lock register for locking parameter and control registers external decoupling for optimum noise performance low power consumption mode in power-down sleep mode 27.2 overview a low power band-gap reference provides atmel ? avr mcu with a highly accurate on-chip voltage reference vref of 1.100v. this reference voltage is used as refer ence for the v-adc, c-adc and brown-out dete ctor. the reference to the adcs uses a buffer with external decoupling capacitor to enable exce llent noise performance with minimum power consumption. the reference voltage v ref_p /v ref_n to the c-adc is scaled to match the full-sca le requirement at the current sense input pins. this configuration also enables concu rrent operation of both v-adc and c-adc. to guarantee ultra low temperature drift after factory calibrati on, the atmel avr mcu features a two-step calibration algorithm . the calibration steps are performed at 25c and 125c. the result is stored in the sign ature row. temperature drift after this calibration is guaranteed by design and characteriza tion to be less than 20 ppm/c from -40c to 125c. the atmel avr mcu has an on-chip temperature sensor for moni toring the die temperature. a voltage complementary-to- absolute-tem perature, v ctat , is generated in the voltage reference circuit and connected to the multiple xer at the v-adc input. this temperature sensor can be used for runtime compensation of temperature drift in both the voltage reference and the on- chip oscillator. to get the absolute tem perature in degrees kelvin, the measured v ctat voltage must be scaled with the v ctat factory calibration values, vtemp slope and vtemp base , stored in the signature row. 27.3 vtemp base and vtemp slope vtemp base is an unsigned 16-bit value. it gives the vadc reading for vtemp(t0) for the adc-conversion used when finding actual temperature. vtemp slope is a signed 8 bit value. it is 4-times the de viation from the typical slope of ?96lsb/k. vtemp slope_hot should be used for temperatures above 25c, while vtemp slope_cold should be used for temperatures below 25c. if the adc reading is below vtemp base use vtemp slope_hot , and if the adc reading is above vtemp base use vtemp slope_cold . when using these values to find actual temperature, use the following formula: adcv temp is the raw adc reading then measuring the vtemp channel. temp base is assumed to be 25c giving: see section 29.8.9 ?reading the signature row from software? on page 173 for details. temp 1 vtemp slope 4 ---------------------------------- 9 6 ? ---------------------------------------------- - adc vtemp vtemp base ? () temp base + = temp[k] 1 vtemp slope 4 ---------------------------------- lsb k ---------- - 96 lsb k ---------- - ? -------------------------------------------------------------------------------- - adc vtemp lsb [] vtemp base lsb [] ? () 298.15 k [] + = 162 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 27-1. reference circuitry 27.4 band gap sample mode the band gap module has two operation modes, continuous mo de and sampled mode. when the band gap module is run in sampled mode, the band gap core and output buffer are switched on and of f at regular time interval s. when the band gap core and output buffer are off, the reference vo ltage is stored on the external capacitor. in continuous mode, the core and output buffer are switched on all the time. the sampled mode is enabl ed automatically in power down sleep mode. in all other operating modes, the continuous mode is used. the timing of the signals in sampled mode is shown in figure 27-2 . the bgsc bits in the bgcsra register control the timing of t_off. for the timing of bg _core_en and bg_buf_en also see section 31. ?electri cal characteristics avr mcu? on page 192ff . figure 27-2. band gap timing the timing of the sampled mode is dependent on the leakage cu rrent from the external capaci tor storing the vref voltage during the off period. for instance a ceramic capacitor of 1 f may have an insulation resistance of ~500m , while a tantalum capacitor of 1 f may have an insulation resistan ce of ~1m . the maximum off period is given by: where cref and r ins are the capacitance and the insulation resistance of the external decoupling capacitor, vref is the bandgap output voltage and is the maximu m allowed variation in vref. as the br own-out detector is the only module using the voltage reference in power down the maximum acce ptable degradation of the bo d level in power-down is the deciding factor when setting vref. setting vref to 15.5mv gives t_off < 7s for a ceramic capacitor and t_off < 14 ms for a tantalum capacitor. timeout settings longer than t_off will violate the vref requirement used in this example. bg control a nd st a tus register a bg st a te m a chine bg interf a ce 1.1v vptat vref_p vref vref_n vref_gnd bg_core_en bg_buf_en bfg reference (core) bg c a libr a tion registers 8-bit d a t a bus bg_sample_mode bg_core_en bg_buf_en t_st a rtup t_st a rtup t_period t_on t_off t_off cref vref r ins vref ---------------------------------------------------------- < vref 163 atmel ata9999 [datasheet] 8096c?avr?01/13 27.5 register description 27.5.1 bgcra - band gap calibration register a notes: 1. the register is only reset by por. 2. the register can be locked by a timed sequence described in the bglr register. bit 7:0 - bgcn[7:0]: band gap calibration nominal the calibration of the nominal value for the band gap module is done by atmel factory calibration. the factory calibrated value is automatically written to this register during chip reset, and should not be changed by the sw. 27.5.2 bgcrb - band gap calibration register b notes: 1. the register is only reset by por. 2. the register can be locked by a timed sequence described in the bglr register. bit 7:0 - bgcl[7:0]: band gap calibration linear the calibration of the linear value for the band gap module is done by atmel factory calibration. the factory calibrated value is automatically written to this register during chip reset, and should not be changed by the sw. 27.5.3 bgcsra - band gap cont rol and status register a notes: 1. due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is required between each ti me the bgcsra register is written. any writing to the bgcsra register during this period will be ignored. 2. the register can be locked by a timed sequence described in the bglr register. 3. after this register has been written, a guard time of 3 ulp oscillator cycles has to be added before entering power- down sleep mode. bit 7:3 - reserved these bits are reserved and will always read as zero. bit 2:0 - bgsc: band gap sample configuration these bits control the sample mode functionality. when bgsc is set to 000, band gap sample mode is disabled and band gap module will remain constant on in all sleep modes. when set to 111, the band gap module will remain con- stant off in power-down sleep mode. when set to other values, the band gap module will enter sample mode in power- down sleep mode. timeout settings for the band gap sample mode are shown in table 27-1 . bit 7 6 5 4 3 2 1 0 (0xd3) bgcn[7:0] bgcra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 7 6 5 4 3 2 1 0 (0xd2) bgcl[7:0] bgcrb read/write r/w r/w r r/w r/w r/w r/w r/w initial value device specific calibration value bit 7 6 5 4 3 2 1 0 (0xd1) ? ? ? ? ? bgcs[2:0] bgcsra read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 164 atmel ata9999 [datasheet] 8096c?avr?01/13 27.5.4 bglr - band gap lock register bit 7:2 - reserved these bits are reserved and will always read as zero. bit 1 - bgple: band gap lock the bgcra, bgcrb and bgcsra registers can be locked from any further software updates. once locked, these reg- isters cannot be accessed until the next hardware reset. to lock these registers, the following algorithm must be followed: 1. in the same operation, writ e a logic one to bgple and bgpl. 2. within the next four clock cycles, in the same operatio n, write a logic zero to bgple and a logic one to bgpl. table 27-1. timeout settings fo r the bandgap sample mode bgsc t_off 000 continuous mode 001 1ms 010 2ms 011 4ms 100 8ms 101 16ms 110 32ms 111 (1) infinite note: 1. this setting is not recommended unless bod is disabled. bit 7 6 5 4 3 2 1 0 (0xd4) ? ? ? ? ? ? bgple bgpl bglr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 165 atmel ata9999 [datasheet] 8096c?avr?01/13 28. debugwire on-c hip debug system 28.1 features complete program flow control emulates all on-chip functions, both digital and analog, except reset pin real-time operation symbolic debugging support (both at c and a ssembler source level, or for other hlls) unlimited number of program break points (using software break points) non-intrusive operation electrical characteristics identical to real device automatic configuration system high-speed operation programming of non-volatile memories 28.2 overview the debugwire on-chip debug system uses a one-wire, bi-directi onal interface to control the program flow, execute avr instructions in the cpu and to progra m the different non-volatile memories. 28.3 physical interface when the debugwire enable (dwen) fuse is progra mmed and lock bits are unprogramm ed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (o pen-drain) bi-directiona l i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 28-1. the debugwire setup figure 28-1 shows the schematic of a target m cu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the oscsel fuse. when designing a system where debugwire will be used, the following observations must be made for correct operation: pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. connecting the reset pin directly to v cc will not work. capacitors connected to the reset pin must be disconnected when using debugwire. all external reset source s must be disconnected. gnd dw (reset) vcc dw 3.0 to 5.5v 166 atmel ata9999 [datasheet] 8096c?avr?01/13 28.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the progra m memory. the instruction replaced by the break instruction will be stored. when program execution is continued, the stor ed instruction will be executed before cont inuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is ch anged. this is automatically handled by avr studio through the debugwire interface. the use of break points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 28.5 limitations of debugwire the debugwire communication pin (dw) is physically located on t he same pin as external reset (reset). an external reset source is therefore not support ed when the debugwire is enabled. a programmed dwen fuse enables some parts of the clock syst em to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. when using debugwire to access the flash (reading/writing), one must make sure the spmcsr register is not locked from before. if spmcsr is locked the result of the operation may not be as expected. 28.6 register description the following section describes the registers used with the debugwire. 28.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the ru nning program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 0x31 (0x51) dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 167 atmel ata9999 [datasheet] 8096c?avr?01/13 29. boot loader support ? read-w hile-write self-programming 29.1 features read-while-write self-programming flexible boot memory size high security (separate boot lock bits for a flexible protection) separate fuse to select reset vector optimized page (1) size code efficient algorithm efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see section 30.5 ?page size? on page 183 ) used dur- ing programming. the page organization does not affect normal operation. 29.2 overview the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates cont rolled by the mcu using a flash- resident boot loader program. the boot load er program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the progr am memory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size o f the boot loader memory is conf igurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexib ility to select different levels of protection. 29.3 application and boot loader flash sections the flash memory is organized in two main sections, the app lication section and the boot loader section. the size of the different sections is configured by the bootsz fuses as shown in section 29.8.13 ?atmel atmega32hve boot loader parameters? on page 176 and figure 29-2 . these two sections can have different level of protection since they have different sets of lock bits. 29.3.1 application section the application section is the se ction of the flash that is used for storing th e application code. the protection level for the application section can be selected by the app lication boot lock bits (boot lock bits 0), see table 30-2 on page 180 . the application section can never store any bo ot loader code since the spm instructio n is disabled when executed from the application section. 29.3.2 bls ? boot loader section while the application section is used for st oring the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level fo r the boot loader section can be selected by the boot loader loc k bits (boot lock bits 1), see table 30-2 on page 180 . 29.4 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a bo ot loader software update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write (rww) section and the no read- while-write (nrww) section. the limit betw een the rww- and nrww sections is given in section 29.8.13 ?atmel atmega32hve boot loader parameters? on page 176 and figure 29-2 on page 169 . the main difference between the two sections is: when erasing or writing a page located inside the rww sect ion, the nrww section can be read during the operation. when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. 168 atmel ata9999 [datasheet] 8096c?avr?01/13 note that the user software can never re ad any code that is locat ed inside the rww section during a boot loader software operation. the syntax ?read-while-write sect ion? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 29.4.1 rww ? read-whi le-write section if a boot loader software update is programming a page inside the rw w section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on -going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programmi ng, the software might end up in an unk nown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sect ion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store prog ram memory control and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see section 29.9.1 ?spmcsr ? store program memory control and status register? on page 178 for details on how to clear rwwsb. 29.4.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updatin g a page in the rww section. when the boot loader code updates the nrww section, the cp u is halted during the entire page erase or page write operation. figure 29-1. read-while-write versus no read-while-write table 29-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no re a d while write (rww) section z-pointer addresses rww section code loc a ted in nrww section c a n be re a d during the oper a tion no re a d while write (rww) section z-pointer addresses nrww section cpu is h a lted during the oper a tion 169 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 29-2. memory sections note: the parameters in the figure above are given in section 29.8.13 ?atmel atmega32hve boot loader parameters? on page 176 . 29.5 boot loader lock bits if no boot loader capability is needed, th e entire flash is available for application code. the boot loader has two separate se ts of boot lock bits which can be set independently. this gives the us er a unique flexibility to select different levels of protec tion. the user can select: to protect the entire flash from a software update by the mcu. to protect only the boot loader flash se ction from a software update by the mcu. to protect only the application flash se ction from a software update by the mcu. allow software update in the entire flash. see table 30-2 on page 180 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general read /write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. boot lo a der fl a sh section applic a tion fl a sh section applic a tion fl a sh section progr a m memory bootsz = ?11? 0x0000 fl a shend re a d-while write section no re a d-while write section end rww st a rt nrww end applic a tion st a rt boot lo a der boot lo a der fl a sh section applic a tion fl a sh section applic a tion fl a sh section progr a m memory bootsz = ?10? 0x0000 fl a shend re a d-while write section no re a d-while write section end rww st a rt nrww end applic a tion st a rt boot lo a der boot lo a der fl a sh section applic a tion fl a sh section applic a tion fl a sh section progr a m memory bootsz = ?01? 0x0000 fl a shend re a d-while write section no re a d-while write section end rww st a rt nrww end applic a tion st a rt boot lo a der boot lo a der fl a sh section applic a tion fl a sh section progr a m memory bootsz = ?00? 0x0000 fl a shend re a d-while write section no re a d-while write section end rww, end applic a tion st a rt nrww, st a rt boot lo a der 170 atmel ata9999 [datasheet] 8096c?avr?01/13 29.6 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via the spi or lin. al ternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the appli cation code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. 29.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see section 30.2 ?fuse bits? on page 181 ), the program counter can be treated as having two different sections. one section, consisting of the least significant bits , is addressing the words within a page, wh ile the most significant bits are addre ssing the pages. this is shown in figure 29-3 . note that the page erase and page write operations are addressed independently. therefor e it is of major importance that the boot loader software addresses the same page in both the page erase and page write op eration. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use t he z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instru ction does also use the z-poin ter to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 29-3. addressing the flash during spm (1) note: 1. the different variables used in figure 29-3 are listed in section 29.8.13 ?atmel atmega32hve boot loader parameters? on page 176 and section 29.8.14 ?atmel atmega64hve boot loader parameters? on page 177 . table 29-2. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 29-5 on page 176 ) note: 1. ?1? means unprogrammed, ?0? means programmed bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 bit pagemsb pcmsb zpagemsb zpcmsb 0 1 15 z-register program counter word address within page page address within the flash 0 pcword pcpage instruction word p a ge 02 01 00 pageend pcword [pagemsb : 0] p a ge progr a m memory 171 atmel ata9999 [datasheet] 8096c?avr?01/13 29.8 self-programming the flash the self-programming routine should always ensure that the pll is in lock before continuing. the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the bu ffer can be filled either before the page erase command or between a page er ase and a page write operation: alternative 1, fill the buffer before a page erase fill temporary page buffer perform a page erase perform a page write alternative 2, fill the buffer after page erase perform a page erase fill temporary page buffer perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for exampl e in the temporary page buffer) before the erase, and then be rewritten. when using alternat ive 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary change s, and then write back the modified data. if alternative 2 is used, it is not possi ble to read the old data while loading sinc e the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page addre ss used in both the page erase and page write operation is addressing the same page. see section 29.8.12 ?simple assembly code example for a boot loader? on page 174 for an assembly code example. 29.8.1 performing page erase by spm to execute page erase, wait until the pll enters lock (1) , set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignor ed. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. page erase to the rww section: the nrww section can be read during the page erase. page erase to the nrww section: the cpu is halted during the operation. note: 1. for the pll lock status, see the pllcsr register. 29.8.2 filling the temporary buffer (page loading) to write an instruction word, wait until the pll enters lock (1) , set up the address in the z-pointer and data in r1:r0, write ?x0000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the c ontent of pcword in the z- register is used to address the data in the temporary buffer. the temporary buffer will auto-era se after a page write operation or by writing the rwwsre bit in spmcs r. it is also erased after a syst em reset. note that it is not possible to write more than on e time to each address without erasing the temporary buffer. any eeprom read or write during an spm operation is not recommended. note: 1. for the pll lock status, see the pllcsr register. 29.8.3 performing a page write to execute page write, wait until the pll enters lock (1) , set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignor ed. the page address must be written to pcpage. other bits in the z- pointer will be ignored during this operation. page write to the rww section: the nrww section can be read during the page write. page write to the nrww section: t he cpu is halted during the operation. note: 1. for the pll lock status, see the pllcsr register. 172 atmel ata9999 [datasheet] 8096c?avr?01/13 29.8.4 using the spm interrupt if the spm interrupt is enabled, the spm in terrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoi d that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in section 19. ?interrupts? on page 70 . 29.8.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updat ed by leaving boot lo ck bit11 unprogrammed. an accidental write to the boot loader itself can corrupt t he entire boot loader, and further software updates might be impossible. if it is not necessary to chan ge the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 29.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed duri ng the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programmi ng the interrupt vector table sh ould be moved to the bls as described in ?interrupts? on page 70 , or the interrupts must be disabled. befo re addressing the rww section after the programming is completed, the us er software must clear the rw wsb by writing the rwwsre. see section 29.8.12 ?simple assembly code example for a boot loader? on page 174 for an example. 29.8.7 setting the lock bits by spm to set the lock bits, wait until the pll enters lock (1) , write the desired data to r0, wr ite ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see following table 30-2 on page 180 for how the different settings of the lock bits affect the flash access. if bits 5:0 in r0 are cleared (zero), the corresponding lock bit will be programmed if an spm inst ruction is executed within fo ur cycles after lbset and spmen are set in spmcsr. the z-pointer is don?t care during this o peration, but for future compatibility it is recommended to load the z-po inter with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7 and 6 in r0 to ?1? when writing the lock bits. when programming the lock bit s the entire flash can be read during the operation. note: 1. for the pll lock status, see the pllcsr register. 29.8.8 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from so ftware. to read the lock bits, load the z-pointer with 0x0001 and set the lbset and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the lbset and spmen bits are set in spmcsr, the value of the lock bits wi ll be loaded in the destination register. the lbset and spmen bits will auto-clear upon completion of reading the lock bits . when lbset and spmen are cleared, lpm will work as described in the ?avr instruction set? description. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointe r with 0x0000 and set the lbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the lbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 30-4 on page 182 for a detailed description and mapping of the fuse low byte. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 7 6 5 4 3 210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 173 atmel ata9999 [datasheet] 8096c?avr?01/13 similarly, when reading the fuse high byte, load 0x0003 in th e z-pointer. when an lpm instruction is executed within three cycles after the lbset and spmen bits are set in the spmcsr, the value of th e fuse high byte (fhb) will be loade d in the destination register as shown below. refer to table 30-3 on page 181 for detailed description and mapping of the fuse high byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unp rogrammed, will be read as one. 29.8.9 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in section 30.3 ?signature bytes? on page 182 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the sigrd and spmen bits are set in spmcsr, the si gnature byte value wi ll be loaded in the destination register. the sigrd and spmen bits will auto-clear 6 cycles after writing to spmcsr, wh ich is locked for furt her writing during these cycles. when sigrd and spmen are cleared, lpm will work as described in the instruction set manual all other addresses are reserved for future use. 29.8.10 spmcsr writing restrictions writing any other combination than ?100001?, ?010001?, ?001001?, ?000101?, ?000011? or ?000001? in the lower six bits will have no effect. spmcsr is locked for writing under the following conditions: one or more of the bits 5:0 in spmcsr is set to 1 during eeprom write (status bit eewe in eecr is set) spmcsr will be cleared at the following events: on completion of successful execution the following instructions: lpm with lbset and spmen set lpm with sigrd and spmen set spm with lbset and spmen set spm with pgers and spmen set spm with pgwrt and spmen set spm with spmen set six cycles after writing spmcsr if any other or no lpm/spm is executed 29.8.11 programming time for flash when using spm the pll oscillator is used to time flash accesses. the pll oscillator should be in lock before writing to the flash. table 29-4 shows the typical programming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 table 29-3. signature bytes word-address byte description 0x0010 vtemp base (16 bit value) 0x0011 vtemp slope (16 bit value); high byte: slope hot, low byte: slope cold table 29-4. spm programming time (1) symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7ms 4.5ms 174 atmel ata9999 [datasheet] 8096c?avr?01/13 29.8.12 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-checking that the pll is in lock is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section ; can be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the ; boot loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 177 atmel ata9999 [datasheet] 8096c?avr?01/13 29.8.14 atmel atmega64hv e boot loader parameters in table 29-5 through table 29-7 , the parameters used in the description of the self-programming are given. table 29-8. boot size configuration (1) bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 256 words 4 0x0000 - 0x7eff 0x7f00 - 0x7fff 0x7eff 0x7f00 1 0 512 words 8 0x0000 - 0x7dff 0x7e00 - 0x7fff 0x7dff 0x7e00 0 1 1024 words 16 0x0000 - 0x7bff 0x7c00 - 0x7fff 0x7bff 0x7c00 0 0 2048 words 32 0x0000 - 0x77ff 0x7800 - 0x7fff 0x77ff 0x7800 note: 1. the different bootsz fuse configurations are shown in figure 29-2 table 29-9. read-while-write limit (1) section pages address read-while-write section (rww) 480 0x0000 - 0x77ff no read-while-write section (nrww) 32 0x7800 - 0x7fff note: 1. for details about these two section, see section 29.4.2 ?nrww ? no read-while-write section? on page 168 and sec- tion 29.4.1 ?rww ? read-while-write section? on page 168 . table 29-10. explanation of different variables used in figure 29-3 on page 170 and the mapping to the z-pointer (1) variable corresponding z-value description pcmsb 14 most significant bit in the progra m counter. (the program counter is 15 bits pc[14:0]) pagemsb 5 most significant bit which is used to address the words within one page (64 words in a page requires six bits pc [5:0]). zpcmsb z15 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equa ls pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[14:6] z14:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) note: 1. z0: should be zero for all spm command s, byte select for the lpm instruction. see section 29.7 ?addressing the flash during self-programming? on page 170 for details about the use of z-pointer dur- ing self-programming. 178 atmel ata9999 [datasheet] 8096c?avr?01/13 29.9 register description 29.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits neede d to control the boot loader operations. bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, a nd the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operati on to the rww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be a ccessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programmi ng operation is completed. alternatively the rwwsb bit will automatically be cleared if a pag e load operation is initiated. bit 5 - sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within th ree clock cycles will read a byte from the signature row into the destination register. see section 29.8.9 ?reading the sign ature row from software? on page 173 for details. an spm instruction within four cycles after sigrd and spmen are se t will have no effect. this operation is reserved for future use and should not be used. bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the r ww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww section, the user software must wa it until the programming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww sectio n. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is se t). if the rwwsre bit is written while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. bit 3 ? lbset: lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within f our clock cycles sets lock bits, according to the data in r0. the data in r1 and the addre ss in the z-pointer are ignored. the lbset bit will automati- cally be cleared upon comp letion of the lock bit set, or after six cycles if no spm instruct ion is executed within four clock cycles. an lpm instruction within three cycles after lbset and spmen are set in the spmcsr register , will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see section 29.8.8 ?reading the fuse and lock bits from software? on page 172 for details. bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the p age address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or after six cycles if no spm instruction is executed within four clock cycles. the cp u is halted during the entire page write operation if the nrww section is addressed. bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from th e high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon completion of a page erase, or after six cycles if no spm inst ruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. bit 765 4 3 210 0x37 (0x57) spmie rwwsb sigrd rwwsre lbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 179 atmel ata9999 [datasheet] 8096c?avr?01/13 bit 0 ? spmen: store pr ogram memory enable this bit enables the spm instruction for the next four clo ck cycles. if written to one together with either rwwsre, lbset, pgwrt? or pgers, the following spm instruction will ha ve a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto-clear upon completion of an spm instruction, or after six cycles if no spm instructi on is executed with in four clock cycles. during page erase and pa ge write, the spmen bit remains high until the operation is completed. 180 atmel ata9999 [datasheet] 8096c?avr?01/13 30. memory programming 30.1 program and data memory lock bits the atmel ? avr mcu provides six lock bits which can be left un programmed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 30-2 . the lock bits can only be erased to ?1? with the chip erase command. table 30-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) ?1? means unprogrammed, ?0? means programmed table 30-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 2 1 0 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 3 0 0 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 1 1 1 no restrictions for spm or lpm accessing the app lication section. 2 1 0 spm is not allowed to write to the application section. 3 0 0 spm is not allowed to write to the applic ation section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 lpm executing from the boot loader sect ion is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while execut ing from the application section. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 181 atmel ata9999 [datasheet] 8096c?avr?01/13 30.2 fuse bits the atmel ? avr mcu has two fuse bytes. table 30-4 and table 30-3 describe briefly the functionality of all the fuses and how they are mapped into the fuse byte. note that the fuses are read as logical zero, ?0?, if they are programmed. 30.2.1 high byte blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm a ccessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the applic ation section, interrupts are disabled while executing from the boot loader section. 4 0 1 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are plac ed in the application section, interrupts are disabled while executing fr om the boot loader section. table 30-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 30-3. fuse high byte bit no fuse high byte description default value 3 dwen enable debugwire 1 (unprogrammed) 2 bootsz1 select boot size 0 (programmed) (1) 1 bootsz0 selecrt boot size 0 (programmed) (1) 0 bootrst select reset vector 1 (unprogrammed) note: 1. the default value of bootsz 1:0 results in maximum boot size. 182 atmel ata9999 [datasheet] 8096c?avr?01/13 30.2.2 low byte the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 30.2.3 latching of fuses the fuse values are latched when the device enters programmi ng mode and changes of the fuse va lues will have no effect until the part leaves programming mode. this doe s not apply to the eesave fuse which will take effect on ce it is programmed. the fuses are also latched on power-up in normal mode. 30.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both programming mode, also when the device is locked. the three bytes reside in a separate address space. the signature bytes of the atmel ? avr mcu are given in table 30-5 . 30.4 calibration bytes the atmel ? avr mcu has calibration bytes for the rc oscillators, inte rnal voltage reference, inte rnal temperature reference and tbd. these bytes reside in the signature address space. see section 29.8.9 ?reading the si gnature row from software? on page 173 for details. table 30-4. fuse low byte bit no fuse low byte description default value 7 wdton watchdog timer always on 1 (unprogrammed) (1) 6 eesave eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) 5 spien enable serial programmable data downloading 0 (programmed, spi programming enabled) 4 boden bod enable 1 (unprogrammed, bod disabled) (5) 3 ckdiv8 (3) divide clock by 8 0 (programmed) 2:1 sut1:0 select start-up time 11 (unprogrammed) (2) 0 oscsel0 oscillator select 1 (unprogrammed) (4) notes: 1. the watchdog is enabled/disabling by writing to the watchdog timer control and status register (wdtcsr). but as a fail-safe, the wdton fuse can be used to force the watchdog to run in system reset mode. 2. the sutx fuse bits are used to configure the startup time from sleep or reset. by default the longest startup time is selected. 3. see section 15.4 ?system clock prescaler? on page 50 for details. 4. when unprogrammed, pll is used as system clock source . programming this fuse is for test pur pose only, and should not be used in application. 5. disabling bod assumed that safe vcc operation is guaranteed by other pa rts of the application. table 30-5. device id part signature bytes address 0x000 0x001 0x002 atmel atmega32hve 0x1e 0x95 0x13 atmel atmega64hve 0x1e 0x96 0x10 183 atmel ata9999 [datasheet] 8096c?avr?01/13 30.5 page size 30.6 serial programming both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations ca n be executed. note, in table 30-8 on page 183 , the pin mapping for spi programming is listed. not all parts us e the spi pins dedicated for the internal spi interface. figure 30-1. serial programming and verify when programming th e eeprom, an auto-erase cycle is built into the self-t imed programming operati on (in the serial mode only) and there is no need to first execute the chip erase inst ruction. the chip erase operat ion turns the content of every memory location in both the prog ram and eeprom arrays into 0xff. depending on the oscsel fuse, a valid clock must be presen t. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2.2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2.2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz table 30-6. no. of words in a page and no. of pages in the flash, atmel avr mcu flash size page size pcword no. of pages pcpage pcmsb 16k words ( 32kbytes) 64 words pc[5:0] 256 pc[13:6] 13 32k words ( 64kbytes) 64 words pc[5:0] 512 pc[14:6] 14 table 30-7. no. of word s in a page and no. of pages in the eeprom, atmel avr mcu eeprom size page size pcword no. of pages pcpage eeamsb 1kbytes 4 bytes eea[1:0] 256 eea[9:2] 9 table 30-8. pin mapping serial programming symbol pins i/o description sck pb5 i serial clock mosi pb6 i serial data in miso pb7 o serial data out gnd reset vcc sck + 3 to 5.5v miso mosi 184 atmel ata9999 [datasheet] 8096c?avr?01/13 30.6.1 serial programming algorithm when writing serial data to the atmel ? avr mcu, data is clocked on the rising edge of sck. when reading data from the at mel avr mcu, data is clock ed on the falling edge of sck. to program and verify the atmel avr mcu in the serial prog ramming mode, the following seque nce is recommended. see four byte instruction formats in following table 30-10 on page 185 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in so me systems, the programmer can not guarantee that sck is held low duri ng power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. for this instruction, minimu m low and high periods for the serial clock (sck) must be doubled. 3. the serial programming instructions will not work if the communication is out of synchro nization. when in sync. the second byte (0x53), will echo back when issuing the third by te of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. wait for at least 1.3 ms after successful programmi ng enable before issuing any programming commands. 5. the flash is programmed one page at a time. the memory p age is loaded one byte at a time by supplying the 5 lsb of the address and data together with the load program memory page instructio n. to ensure correct loading of the page, the data low byte must be loaded before data high by te is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 6 msb of the address. if polling (rdy/bsy) is not used, the user must wait at least t wd_flash before issuing the next page. (see table 30-9 .) access- ing the serial programming interface before the flash write operation complete s can result in incorrect programming. 6. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the appro- priate write instruction. an eeprom memory location is first automatically erased before new data is written. if polling (rdy/bsy) is not used, t he user must wait at least t wd_eeprom before issuing the next byte. (see table 30-9 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by supply- ing the 2 lsb of the address and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading the write eeprom memory page inst ruction with the 6 m sb of the address. when using eeprom page access only by te locations loaded with the load eeprom memory page instruction is altered. the remaining locations remain unchanged. if polling (rdy/bsy) is not used, the used must wait at least t wd_eeprom before issuing the next page (see table 30-9 on page 184 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 7. any memory location can be verified by using the read in struction which returns the content at the selected address at serial output miso. 8. at the end of the programming session, reset can be set high to commence normal operation. 9. power-off sequence (if needed): set reset to ?1?. turn v cc power off. table 30-9. minimum wait delay before writ ing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 4.0ms t wd_erase 4.0ms t wd_fuse 4.5ms 185 atmel ata9999 [datasheet] 8096c?avr?01/13 30.6.2 serial programming instruction set table 30-10 on page 185 and figure 30-2 on page 186 describes the instruction set. if the lsb in rdy/bsy data byte out is ?1?, a programming operation is still pending. wa it until this bit re turns ?0? before th e next instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buffer, prog ram the eeprom page, see figure 30-2 on page 186 . table 30-10. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 adr msb adr lsb high data byte in load program memory page, low byte $40 adr msb adr lsb low data byte in load eeprom memory page (page access) $c1 adr msb adr lsb data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 adr msb adr lsb data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 adr lsb data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions(6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 adr msb adr lsb data byte in write eeprom memory page (page access) $c2 adr msb adr lsb $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in notes: 1. not all instructions are applicable for all parts. 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the correspondig section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use word addr ess. this address may be random within the page range. 7. see htt://www.atmel.com/avr for application notes regarding programming and programmers. 186 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 30-2. serial programming instruction example 30.7 high-voltage serial programming this section describes how to program a nd verify flash program memory, eeprom data memory, lock bits and fuse bits in the atmel ? avr mcu. figure 30-3. high-voltage serial programming byte 1 byte 2 byte 3 byte 4 p a ge 0 p a ge 1 p a ge 2 adr lbs adr mbs bit 15 b 0 bit 15 b 0 byte 1 byte 2 byte 3 byte 4 adr lbs adr mbs p a ge n-1 progr a m memory / eeprom memory p a ge buffer p a ge number p a ge offset lo a d progr a m memory p a ge (high/low byte)/ lo a d eeprom memory p a ge (p a ge a ccess) write progr a m memory p a ge / write eeprom memory p a ge gnd reset vcc sdi sdo sii sci + 3.0 to 3.5v prog_en a ble [0] + 11.5 to 12.5v 187 atmel ata9999 [datasheet] 8096c?avr?01/13 30.8 high-voltage serial programming algorithm to program and verify the atmel ? avr mcu in the high-voltage serial programming mode, the following sequence is recommended (see instruction formats in table 30-14 ): 30.8.1 enter high-voltage serial programming mode the following algorithm puts the device in serial (high-voltage) programming mode: 1. set prog_enable pins listed in table 30-12 on page 187 to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 3.0 - 3.5v between v cc and gnd. ensure that v cc reaches at least 1.8v within the next 20 s. 3. wait 20 - 60 s, and apply v hrst - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least t hvrst after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. release prog_enable[1] pin to avoid driv e contention on the prog_enable[1]/sdo pin. 6. wait at least 1.3 ms before giving any serial instructions on sdi/sii. 7. if the rise time of the v cc is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 8. set prog_enable pins listed in table 30-12 on page 187 to ?0000?, reset pin to 0v and v cc to 0v. 9. apply 3.0 - 3.5v between v cc and gnd. 10. monitor v cc , and as soon as v cc reaches 0.9 - 1.1v, apply v hrst - 12.5v to reset. 11. keep the prog_enable pins unchanged for at least t hvrst after the high-voltage has been applied to ensure the prog_enable signature has been latched. 12. release prog_enable[1] pin to avoid driv e contention on the prog_enable[1]/sdo pin. 13. wait until v cc actually reaches 3.0 - 3.5v. 14. wait at least 1.3ms before giving any serial instructions on sdi/sii. table 30-11. pin name mapping signal name in high-voltage serial programming mode pin name i/o function sdo pb5 o serial data output sdi pb6 i serial data input sii pb7 i serial instruction input sci pb2 i serial clock input (min. 2/f ck period) table 30-12. pin values used to enter programming mode pin name symbol value pb4 prog_enable[0] 0 pb5 prog_enable[1] 0 pb6 prog_enable[2] 0 pb7 prog_enable[3] 0 table 30-13. high-voltage reset characteristics supply voltage reset pin high-vol tage threshold minimum high-voltage period for latching prog_enable v cc v hvrst t hvrst 3.0v 11.5v 10 s 3.5v 11.5v 10 s 188 atmel ata9999 [datasheet] 8096c?avr?01/13 30.8.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. the command needs only be loaded once when writing or reading multiple memory locations. skip writing the data value 0xff that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 30.8.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not chan ged. a chip erase must be performed before the flash and/or eeprom are re-programmed. note: 1. the eeprom memory is preserved during chip erase if the eesave fuse is programmed. 1. load command ?chip erase? (see table 30-14 ). 2. wait after instr.3 until sdo goes high for the ?chip erase? cycle to finish. 3. load command ?no operation?. 30.8.4 programming the flash the flash is organized in pages, see table 30-10 on page 185 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: 1. load command ?write flash? (see table 30-14 ). 2. load flash page buffer. 3. load flash high address and program page. wait after instr. 3 until sdo goes high for the ?page programming? cycle to finish. 4. repeat 2 through 3 until the entire flash is pr ogrammed or until all data has been programmed. 5. end page programming by load ing command ?no operation?. when writing or reading serial data to the atmel ? avr mcu, data is clocked on the rising edge of the serial clock, see figure 30-5 , figure 31-5 and section 31.8.2 ?high-voltage serial programming? on page 202 for details. figure 30-4. addressing the flash which is organized in pages pagemsb pcmsb program counter word address within page page address within the flash pcword pcpage instruction word p a ge 02 01 00 pageend pcword [pagemsb : 0] p a ge progr a m memory 189 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 30-5. high-voltage serial programming waveforms 30.8.5 programming the eeprom the eeprom is organized in pages, see section 31.8.2 ?high-voltage serial programming? on page 202 . when programming the eeprom, the data is latched into a page buffer. this a llows one page of da ta to be programmed simultaneously. the programming algorithm for the eeprom da ta memory is as follows (refer to table 30-14 on page 190 ): 1. load command ?write eeprom?. 2. load eeprom page buffer. 3. program eeprom page. wait after in str. 2 until sdo goes high for the ?page programming? cycle to finish. 4. repeat 2 through 3 until the entire eeprom is programmed or until all data has been programmed. 5. end page programming by loading command ?no operation?. 30.8.6 reading the flash the algorithm for reading the flash memory is as follows (refer to table 30-14 on page 190 ): 1. load command "read flash". 2. read flash low and high bytes. the contents at the selected address are available at serial output sdo. 30.8.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to table 30-14 on page 190 ): 1. load command ?read eeprom?. 2. read eeprom byte. the contents at the selected address are available at serial output sdo. 30.8.8 programming and reading the fuse and lock bits the algorithms for programming and reading the fuse low/high bits and lock bits are shown in table 30-14 on page 190 . 30.8.9 reading the signature bytes and calibration byte the algorithms for reading the signature bytes and calibration byte are shown in table 30-14 on page 190 . 0123 msb msb msb 45678910 sdi sii sdo sci 190 atmel ata9999 [datasheet] 8096c?avr?01/13 30.8.10 power-off sequence exit programming mode by powering the device down, or by bringi ng reset pin to 0v. table 30-14. high-voltage serial prog ramming instruction set for atmel ? avr mcu instruction instruction format operation remarks instr.1/5 instr.2/6 instr.3 instr.4 chip erase sdi sii sdo 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx load ?write flash? command sdi sii sdo 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx load flash page buffer sdi sii sdo 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_ eeee _ eeee _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_ dddd _ dddd _00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1101_00 x_xxxx_xxxx_xx sdi sii sdo 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx load flash high address and program page sdi sii sdo 0_ aaaa _ aaaa _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx load ?read flash? command sdi sii sdo 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx read flash low and high bytes sdi sii sdo 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_ aaaa _ aaaa _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q _ qqqq _ qqq x_xx sdi sii sdo 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p _ pppp _ ppp x_xx load ?write eeprom? command sdi sii sdo 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx load eeprom page buffer sdi sii sdo 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_ eeee _ eeee _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx program eeprom page sdi sii sdo 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx write eeprom byte sdi sii sdo 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_ eeee _ eeee _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx sdi sii sdo 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx load ?read eeprom? command sdi sii sdo 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx 191 atmel ata9999 [datasheet] 8096c?avr?01/13 note: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don?t care, c = lock bit byte, l = fuse low byte, h = fuse high byte. notes: 1. for page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address. 2. for page sizes less than 256 bytes, parts of t he address (bbbb_bbbb) will be parts of the page address. the eeprom is written page-wise. but only the bytes that are loaded into the page are actually written to the eeprom. page- wise eeprom access is more efficient when mu ltiple bytes are to be written to the same page. note that auto-erase of eeprom is not available in high-voltage seri al programming, only in spi programming. read eeprom byte sdi sii sdo 0_ bbbb _ bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_ aaaa _ aaaa _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q _ qqqq _ qqq 0_00 write fuse high byte sdi sii sdo 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ hhhh_hhhh _00 0_0010_1100_11 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx wait after instr. 4 until sdo goes high. write ?0? to program the fuse bits. write fuse low byte sdi sii sdo 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ iiii _ iiii _00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx wait after instr. 4 until sdo goes high. write ?0? to program the fuse bit. write lock bit byte sdi sii sdo 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_cccc_cccc_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx wait after instr. 4 until sdo goes high. write ?0? to program the lock bit. read fuse high byte sdi sii sdo 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 h_hhhh_hhhx_xx reading ?0? means the fuse bit is programmed. read fuse low byte sdi sii sdo 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 i _ iiii _ iii x_xx reading ?0? means the fuse bit is programmed. read lock bit byte sdi sii sdo 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 c_cccc_cccx_xx reading ?0? means the lock bit is programmed. read signature row low byte sdi sii sdo 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ bbbb_bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q _ qqqq _ qqq x_xx repeats instr 2 4 for each signature low byte address. read signature row high byte sdi sii sdo 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ aaaa_aaaa _00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p _ pppp _ ppp x_xx repeats instr 2 4 for each signature high byte address. load ?no operation? command sdi sii sdo 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx table 30-14. high-voltage serial prog ramming instruction set for atmel ? avr mcu (continued) instruction instruction format operation remarks instr.1/5 instr.2/6 instr.3 instr.4 192 atmel ata9999 [datasheet] 8096c?avr?01/13 31. electrical characteristics avr mcu unless otherwise noted all parameters in th is section are valid for a supply voltage of 3.0v to 3.6v and a junction temperature range from ?40c to +125c. all voltages refe r to pin gnd = 0 if not otherwise specified. 31.1 power consumption characteristics t a = ?40c to 125c unless otherwise noted no. parameters test conditions pin symbol min typ max unit type* 1.1 active current all i/o disabled. wut, wdt, bandgap enabled 14.33mhz vcc, avcc 4.5 5.5 6.5 ma a 1.2 all i/o disabled. wut, wdt, bandgap enabled 1.79mhz 1.7 ma c 1.3 all i/o enabled, vadc (batt channel) and cadc 256x gain. 512khz adc clock, wut, wdt, bandgap enabled 14.33mhz 6.0 7.2 9.0 ma a 1.4 idle current all i/o disabled. wut, wdt, bandgap enabled, clkdiv=1 14.33mhz 800 a c 1.5 all i/o disabled. wut, wdt, bandgap enabled 1.79mhz 500 800 1000 a a 1.6 all i/o enabled, vadc (batt channel) and cadc 256x gain. 512khz adc clock, wut, wdt, bandgap enabled 14.33mhz 1800 2600 3500 a a 1.7 reset current device in reset vcc, avcc 350 500 1000 a a 1.8 power save current wut, wdt, bandgap enabled vcc, avcc 90 105 150 a a 1.9 cadc with 128khz clock - 256x gain, wut, wdt, bandgap enabled 200 450 650 a 1.10 vadc (batt channel) and cadc 256x gain. 512khz adc clock, wut, wdt, bandgap enabled 1400 c 1.11 power down current wut, wdt, bandgap (bgsc = 011) enabled 8 15 50 a wut, wdt, bandgap (bgsc = 111) enabled 0.3 40 a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 193 atmel ata9999 [datasheet] 8096c?avr?01/13 31.2 bandgap curvature compensated (bgcc) 31.2.1 dc characteristics no. parameters test conditions pin symbol min typ max unit type* 2.1 initial accuracy t a = 25c vref 1.097 1.1 1.103 v a 2.2 temperature drift after 2 temp factory calibration vref ?20 5 +20 ppm/c a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 31.2.2 ac characteristics no. parameters test conditions pin symbol min typ max unit type* 2.4 vref startup time from power-off state vref = 0 - 1.1v, cref = 1.0f 2 5 ms c 2.5 vref ripple, toff = 32ms measured at 25c with 10m load 5 10 mv c *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 31.2.3 die temperature measurement no. parameters test conditions pin symbol min typ max unit type* 2.6 measurement of internal temperature; accuracy temperature measurement according to section 27.3 on page 161 2 5 c a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 194 atmel ata9999 [datasheet] 8096c?avr?01/13 31.3 adc characteristics 31.3.1 voltage adc characteristi cs - operating conditions t a = ?40c to +125c, v cc = 3v to 3.6v, v ref = 1.1v, unless otherwise noted. no. parameters test conditions pin symbol min typ max unit type* 3.1 fsr, resolution and conversion rates full scale range 0 1.1 v d 3.2 number of bits (unsigned) instantaneous output 16 bits d 3.3 accumulate output 16 17 d 3.4 1 lsb instantaneous output 16.8 v d 3.5 accumulate output 16.8 d 3.6 inst. output conversion rate no chopper normal mode 1000 8000 hz d 3.7 no chopper low-power mode 250 2000 d 3.8 fast chopper normal mode 332 2667 d 3.9 fast chopper low-power mode 83 667 d 3.10 slow chopper normal mode 1000 8000 d 3.11 slow chopper low-power mode 250 2000 d 3.12 acc. output conversion rate no chopper normal mode 1.96 2000 d 3.13 no chopper low-power mode 0.49 500 d 3.14 fast chopper normal mode 0.64 667 d 3.15 fast chopper low-power mode 0.16 167 d 3.16 slow chopper normal mode 1.96 1333 d 3.17 slow chopper low-power mode 0.49 333 d 3.18 pv2/nv2 inl without divider range 0v to 1v 0.008 0.03 %fsr c range 0.4v to 0.6v 0.008 0.01 %fsr c 3.19 inl incl divider range 9.6v to 14.4v 0.003 0.006 %f s r c 3.20 offset (1) no chopper 101 672 v c 3.21 fast chopper, ic output 0 17 v c 3.22 slow chopper, ac ouput 0 17 v c 3.23 offset drift (1) no chopper 0.2 0.5 v/c c 3.24 fast chopper, ic output 0 17 v c 3.25 slow chopper, ac ouput 0 17 v c 3.26 gain drift including vref drift, range 0v to 1v 5 20 ppm/c c 3.27 including vref drift, range 0.4v to 0.6v 5 20 ppm/c c 3.28 equivalent input impedance normal mode 100 m d 3.29 lp mode 60 d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. measured in test mode with inputs shorted 195 atmel ata9999 [datasheet] 8096c?avr?01/13 3.30 adc0/sgnd; adc1/sgnd inl range 0v to 1v 0.02 0.06 %fsr c 3.31 offset no chopper 34 336 v c 3.32 fast chopper 0 17 v c 3.33 slow chopper 0 17 v c 3.34 adc0/sgnd; adc1/sgnd offset drift no chopper 0.3 0.8 v/c c 3.35 fast chopper 0 17 v c 3.36 slow chopper 0 17 v c 3.37 gain drift including vref drift, nom mode, range 0v to 1v 5 25 ppm/c c 3.38 including vref drift, lp mode, range 0v to 1v 5 25 ppm/c c 3.39 vref measurement according to vdac diagnosis mode, see section 26.5 on page 149 vadc reading ?4% 0.55 +4% v a 3.40 pull-up pv2/nv2 open diagnosis register adcre vadpdm[1:0]=11 pv2, nv 22 k a 31.3.1 voltage adc characteristics - operating conditions (continued) t a = ?40c to +125c, v cc = 3v to 3.6v, v ref = 1.1v, unless otherwise noted. no. parameters test conditions pin symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. measured in test mode with inputs shorted 196 atmel ata9999 [datasheet] 8096c?avr?01/13 31.3.2 current adc characteri stics - operating conditions t a = -40 to 125c unless otherwise noted. no. parameters test conditions pin symbol min typ max unit type* 3.42 fsr, resolution and conversion rates full scale range after gain amplifier at adc input -660 660 mv d 3.43 number of bits instantaneous output 16 bits d 3.44 accumulate output 16 18 d 3.45 1 lsb referred to 16-bit result pga gain = 4 5.035 v d 3.46 pga gain = 8 2.5175 d 3.47 pga gain = 16 1.2588 d 3.48 pga gain = 32 0.6294 d 3.49 pga gain = 64 0.3147 d 3.50 pga gain = 128 0.1573 d 3.51 pga gain = 256 0.0787 d 3.52 inst. output conversion rate (1) no chopper normal mode 1000 8000 hz d 3.53 no chopper low-power mode 250 2000 d 3.54 fast chopper normal mode 332 2667 d 3.55 fast chopper low-power mode 83 667 d 3.56 slow chopper normal mode 1000 8000 d 3.57 slow chopper low-power mode 250 2000 d 3.58 acc. output conversion rate (1) no chopper normal mode 1.96 2000 d 3.59 no chopper low-power mode 0.49 500 d 3.60 fast chopper normal mode 0.64 667 d 3.61 fast chopper low-power mode 0.16 167 d 3.62 slow chopper normal mode 1.96 1333 d 3.63 slow chopper low-power mode 0.49 333 d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. conversion rate scales proportionally to frequency in slowrc oscillator 2. measured in power save, 256x gain 3. measured with pi-ni shorted 197 atmel ata9999 [datasheet] 8096c?avr?01/13 3.64 accuracy inl 90% fsr, 256x gain 0.15 0.3 %fsr c 3.65 90% fsr, 4x gain 0.02 0.06 c 3.66 offset (referred to input) (2)(3) no chopper 35 150 v c 3.67 fast chopper 2.5 5 c 3.68 slow chopper 2.5 5 c 3.69 offset drift (referred to input) (2)(3) no chopper 80 300 nv/c c 3.70 fast chopper 6 20 c 3.71 slow chopper 6 20 c 3.72 uncompensated gain error including vref drift, pga gain = 4 0.05 0.1 %fsr c 3.73 including vref drift, pga gain = 256 1.5 2 c 3.74 gain drift including vref drift, pga gain = 4 5 25 ppm/c c 3.75 including vref drift, pga gain = 256 10 50 c 3.76 input impedance normal mode 100 k d 3.77 lp mode 60 d 3.78 vrefp_test measurement according to section 26.5 on page 149 cadc reading ?4% 0.33 +4% v a 3.79 p u ll- u p pi/ni open diagno s i s regi s ter adcrd cadpdm[1:0]=11 pi, ni 22 k a 31.3.2 current adc characteristics - operating conditions (continued) t a = -40 to 125c unless otherwise noted. no. parameters test conditions pin symbol min typ max unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. conversion rate scales proportionally to frequency in slowrc oscillator 2. measured in power save, 256x gain 3. measured with pi-ni shorted 198 atmel ata9999 [datasheet] 8096c?avr?01/13 31.4 oscillator characteristics t a = -40 to 125c, v cc = 3.3v unless otherwise noted. no. parameters test conditions pin symbol min typ max unit type* 4.1 slow rc oscillator frequency reference frequency: slow rcosc ?4% 128 +4% khz a 4.2 temperature drift centered at 25c ?1 +1 % a 4.3 pll frequency multiplication factor 112 d 4.4 startup time from pdown/psave latency from module enabled until first clock edge (ref = 128khz) 25 40 s c 4.5 frequency settling time setting to 99% of target 180 250 s c 4.6 ultra low power rc oscillator frequency, initial accuracy ?20% 131 +20% khz a 4.7 temperature drift centered at 25c. vcc = 3.3v ?5 +5 % a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 31.5 external interrupt characteristics asynchronous external in terrupt characteristics no. parameters test conditions pin symbol min typ max unit type* 5.1 pulse width for asynchronous external interrupt t int 500 2000 ns c *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 199 atmel ata9999 [datasheet] 8096c?avr?01/13 31.6 general i/o lines characteristics 31.6.1 port a and b characteristics t a = -40 to 125c, v cc = 3.3v (unless otherwise noted) no. parameters test conditions pin symbol min. typ. max. unit type* 6.1 input low voltage, except reset pin pa[1:0], pb[7:0] v il ?0.5 0.3v cc (1) v c 6.2 input low voltag e, reset pin reset v il1 0.3v cc (1) v c 6.3 input high voltage, except reset pin pa[1:0], pb[7:0] v ih 0.6v cc (2) v cc + 0.5 v c 6.4 input high voltage, reset pin reset v ih1 0.9v cc (2) v cc + 0.5 v c 6.5 output low voltage (3) i ol = 5ma pa[1:0], pb[7:0] v ol 0.5 v a 6.6 output high voltage (4) i oh = 2 ma pa[1:0], pb[7:0] v oh 2.3 v a 6.7 input leakage current i/o pin pin low (absolute value) pa[1:0], pb[7:0] i il 1 a a 6.8 input leakage current i/o pin pin high (absolute value) pa[1:0], pb[7:0] i ih 1 a a 6.9 reset pull-up resistor reset r rst 30 60 k a 6.10 i/o pin pull-up resistor pa[1:0], pb[7:0] r pu 20 50 k a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where th e pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (5 ma at v cc = 3.3v) under steady state conditions (non- transient), the following must be observed: - the sum of all iol should not exceed 20 ma. if iol exceeds the test condition, vol may exceed the related specification. pi ns are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (2 ma at v cc = 3.3v) under steady state conditions (non- transient), the following must be observed: - the sum of all ioh should not exceed 2 ma. 200 atmel ata9999 [datasheet] 8096c?avr?01/13 31.7 spi timing characteristics see figure 31-1 on page 200 and figure 31-2 on page 201 for details. figure 31-1. spi interface timing requirements (master mode) 31.7.1 spi timing parameters no. parameters test conditions pin symbol min. typ. max. unit type* 7.1 sck period master see ns d 7.2 sck high/low master 50% duty d 7.3 rise/fall time master 3.6 d 7.4 setup master 10 d 7.5 hold master 10 d 7.6 out to sck master 0.5 t sck d 7.7 sck to out master 10 d 7.8 sck to out high master 10 d 7.9 ss low to out slave 15 d 7.10 sck period slave 4 t ck + d 7.11 sck high/low (1) slave 2 t ck + d 7.12 rise/fall time slave 1.6 s d 7.13 setup slave 10 ns d 7.14 hold slave t ck d 7.15 sck to out slave 15 d 7.16 sck to ss high slave 20 d 7.17 ss high to tri-state slave 10 d 7.18 ss low to sck slave 20 d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. refer to section 30.6 ?serial programming? on page 183 for serial programming requirements. 6 msb ss sck (cpol = 0) sck (cpol = 1) miso (d a t a output) mosi (d a t a output) msb lsb lsb ... ... 45 8 7 1 2 2 3 201 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 31-2. spi interface timing requirements (slave mode) 31.8 programming characteristics 31.8.1 serial programming figure 31-3. serial programming timing figure 31-4. serial programming waveforms 9 msb ss sck (cpol = 0) sck (cpol = 1) mosi (d a t a output) miso (d a t a output) msb lsb lsb ... ... 13 14 17 15 10 16 11 11 12 mosi sck miso t ovsh t shox t shsl t slsh t sliv serial data input (mosi) serial data output (miso) serial clock input (sck) sample msb lsb msb lsb 202 atmel ata9999 [datasheet] 8096c?avr?01/13 31.8.2 high-voltage serial programming figure 31-5. high-voltage se rial programming timing 31.8.1.1serial programming characteristics t a = -10c to 70c, v cc = 3.0 - 5.5v (unless otherwise noted) no. parameters test conditions pin symbol min typ max unit type* 8.1 oscillator frequency (atmel avr mcu) 1/t clcl 0 4 mhz d 8.2 oscillator period (atmel avr mcu) t clcl 250 ns d 8.3 sck pulse width high t shsl 2.2 t clcl (1) d 8.4 sck pulse width low t slsh 2.2 t clcl (1) d 8.5 mosi setup to sck high t ovsh t clcl d 8.6 mosi hold after sck high t shox 2 t clcl d 8.7 sck low to miso valid t sliv 15 ns d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. 2.2 t clcl for f ck < 12mhz, 3.3 t clcl for f ck 12mhz sdi, sii sci sdo t ivsh t shix t shsl t slsh t shov 31.8.2.1high-voltage serial programming characteristics t a = 25c 10%, v cc = 3.3v 10% (unless otherwise noted) no. parameters test conditions pin symbol min typ max unit type* 8.8 sci (pc0) pulse width high t shsl 1/f ck ns d 8.9 sci (pc0) pulse width low t slsh 1/f ck ns d 8.10 sdi (pb2), sii (pb3) valid to sci (pc0) high t ivsh 50 ns d 8.11 sdi (pb2), sii (pb3) hold after sci (pc0) high t shix 50 ns d 8.12 sci (pc0) high to sdo (pb1) valid t shov 16 ns d 8.13 wait after instr. 3 for write fuse bits t wlwh_pfb 2.5 ms d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 203 atmel ata9999 [datasheet] 8096c?avr?01/13 32. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) vadac3 vadac3[31:24] 158 (0xf5) vadac2 vadac2[23:16] 158 (0xf4) vadac1 vadac1[15:8] 158 (0xf3) vadac0 vadac0[7:0] 158 (0xf2) vadich vadich[15:8] 158 (0xf1) vadicl vadicl[7:0] 158 (0xf0) cadac3 cadac3[31:24] 159 (0xef) cadac2 cadac2[23:16] 159 (0xee) cadac1 cadac1[15:8] 159 (0xed) cadac0 cadac0[7:0] 159 (0xec) cadich cadich[15:8] 159 (0xeb) cadicl cadicl[7:0] 159 (0xea) cadrclh cadrclh[15:8] 157 (0xe9) cadrcll cadrcll[7:0] 157 (0xe8) adimr ? ? vadacie vadicie ? cadrcie cadacie cadicie 157 (0xe7) adifr ? ? vadacif vadicif ? cadrcif cadacif cadicif 156 (0xe6) adcre vaden ? vadrefs vadpdm1 vadpdm0 vamux2 vamux1 vamux0 155 (0xe5) adcrd ? ? cadg2 cadg1 cadg0 cadpdm1 cadpdm0 caddsel 154 (0xe4) adcrc caden ? cadrcm1 cadrcm0 cadrct3 cadrct2 cadrct1 cadrct0 153 (0xe3) adcrb ? ? ? adides1 adides0 adades2 adades1 adades0 152 (0xe2) adcra ? ? ? ? adpsel adcms1 adcms0 cksel 151 (0xe1) adscsrb ? vadicps vadacrb vadicrb ? cadicps cadacrb cadicrb 150 (0xe0) adscsra ? ? ? ? ? sbsy scmd1 scmd0 149 (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) pbov pbovce ? ? ?pboe3 ? ?pboe0 89 (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) pllcsr ? ?swenlock ? ? pllcif pllcie 51 (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) bglr ? ? ? ? ? ? bgple bpgl 164 (0xd3) bgcra bgcn[7:0] 163 (0xd2) bgcrb bgcl[7:0] 163 (0xd1) bgcsra ? ? ? ? ?bgsc[2:0] 163 (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? notes: 1. for compatibility with future devices, reserved bits shou ld be written to zero if acce ssed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bi t-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/ o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 must be added to these addresses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 204 atmel ata9999 [datasheet] 8096c?avr?01/13 (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) lindat ldata[7:0] 137 (0xc9) linsel ? ? ? ?lainc lindx[2:0] 137 (0xc8) linidr lp1 lp0 lid5/lidl1 lid4/lidl0 lid[3:0] 136 (0xc7) linldr ltxdl[7:0] 136 (0xc6) linbrh ? ? ? ?ldiv[11:8] 135 (0xc5) linbrl ldiv[7:0] 135 (0xc4) linbtr ldisr ? lbt[5:0] 135 (0xc3) linerr labort ltoerr loverr lferr lserr lperr lcerr lberr 134 (0xc2) linenir ? ? ? ? lenerr lenidok lentxok lenrxok 134 (0xc1) linsir lidst[2:0] lbusy lerr lidok ltxok lrxok 133 (0xc0) lincr lswres lin13 lconf[1:0] lena lcmd[2:0] 132 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) reserved ? ? ? ? ? ? ? ? (0xbc) reserved ? ? ? ? ? ? ? ? (0xbb) reserved ? ? ? ? ? ? ? ? (0xba) reserved ? ? ? ? ? ? ? ? (0xb9) reserved ? ? ? ? ? ? ? ? (0xb8) reserved ? ? ? ? ? ? ? ? (0xb7) reserved ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? 32. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be che cked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i /o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 must be added to these addresses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 205 atmel ata9999 [datasheet] 8096c?avr?01/13 (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) reserved ? ? ? ? ? ? ? ? (0x8a) reserved ? ? ? ? ? ? ? ? (0x89) ocr1b timer/counter1 ? output compare register b 106 (0x88) ocr1a timer/counter1 ? output compare register a 106 (0x87) reserved ? ? ? ? ? ? ? ? (0x86) reserved ? ? ? ? ? ? ? ? (0x85) tcnt1h timer/counter1 (8 bit) high byte 106 (0x84) tcnt1l timer/counter1 (8 bit) low byte 105 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c ? ? ? ? ? ? ics11 ics10 105 (0x81) tccr1b ? ? ? ? ? cs12 cs11 cs10 92 (0x80) tccr1a tcw1 icen1 icnc1 ices1 ? ? ? wgm10 104 (0x7f) reserved ? ? ? ? ? ? ? ? (0x7e) didr0 ? ? ? ? ? ? pa1did pa0did 160 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) reserved ? ? ? ? ? ? ? ? (0x7b) reserved ? ? ? ? ? ? ? ? (0x7a) reserved ? ? ? ? ? ? ? ? (0x79) reserved ? ? ? ? ? ? ? ? (0x78) reserved ? ? ? ? ? ? ? ? (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ? ? ? icie1 ocie1b ocie1a toie1 106 (0x6e) timsk0 ? ? ? ? icie0 ocie0b ocie0a toie0 106 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) pcmsk1 pcint[9:2] 77 (0x6b) pcmsk0 ? ? ? ? ? ? pcint[1:0] 77 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ? ? ? isc01 isc00 75 (0x68) pcicr ? ? ? ? ? ? pcie1 pcie0 76 (0x67) sosccalb slow rc oscillator calibration register b 51 32. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits shou ld be written to zero if acce ssed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bi t-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/ o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 must be added to these addresses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 206 atmel ata9999 [datasheet] 8096c?avr?01/13 (0x66) sosccala slow rc oscillator calibration register a 51 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr0 ? ? prlin prspi prtim1 prtim0 57 (0x63) wdtclr ? ? ? ? ? wdcl1 wdcl0 wdcle (0x62) wutcsr wutif wutie ? wutr wute wutp2 wutp1 wutp0 (0x61) clkpr clkpce ? ? ? ? ? clkps1 clkps0 52 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 65 0x3f (0x5f) sreg i t h s v n z c 36 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 38 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 38 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr ? ? sigrd ctpb rflb pgwrt pgers spmen 178 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? ?ckoepud ? ? ivsel ivce 88 / 52 0x34 (0x54) mcusr ? ? ? ocdrf wdrf bodrf extrf porf 65 0x33 (0x53) smcr ? ? ? ? sm[2:0] se 56 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) dwdr debugwire data register 166 0x30 (0x50) reserved ? ? ? ? ? ? ? ? 0x2f (0x4f) tccr0c ? ? ? ? ? ? ics01 ics00 105 0x2e (0x4e) spdr spi data register 115 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x 115 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 114 0x2b (0x4b) gpior2 general purpose i/o register 2 47 0x2a (0x4a) gpior1 general purpose i/o register 1 47 0x29 (0x49) ocr0b timer/counter0 output compare register b 106 0x28 (0x48) ocr0a timer/counter0 output compare register a 106 0x27 (0x47) tcnt0h timer/counter0 (8 bit) high byte 106 0x26 (0x46) tcnt0l timer/counter0 (8 bit) low byte 105 0x25 (0x45) tccr0b ? ? ? ? ? cs02 cs01 cs00 92 0x24 (0x44) tccr0a tcw0 icen0 icnc0 ices0 ? ? ? wgm00 104 0x23 (0x43) gtccr tsm ? ? ? ? ? ? psrsync 0x22 (0x42) eearh ? ? ? ? ? ? eeprom high byte 44 0x21 (0x41) eearl high byte only 1 bit 44 0x20 (0x40) eedr eeprom data register 44 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 44 0x1e (0x3e) gpior0 general purpose i/o register 0 47 0x1d (0x3d) eimsk ? ? ? ? ? ? ? int0 75 0x1c (0x3c) eifr ? ? ? ? ? ? ? intf0 76 0x1b (0x3b) pcifr ? ? ? ? ? ? pcif1 pcif0 76 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) reserved ? ? ? ? ? ? ? ? 0x16 (0x36) tifr1 ? ? ? ? icf1 ocf1b ocf1a tov1 107 0x15 (0x35) tifr0 ? ? ? ? icf0 ocf0b ocf0a tov0 107 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 32. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be che cked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i /o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 must be added to these addresses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 207 atmel ata9999 [datasheet] 8096c?avr?01/13 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) reserved ? ? ? ? ? ? ? ? 0x0a (0x2a) reserved ? ? ? ? ? ? ? ? 0x09 (0x29) reserved ? ? ? ? ? ? ? ? 0x08 (0x28) reserved ? ? ? ? ? ? ? ? 0x07 (0x27) reserved ? ? ? ? ? ? ? ? 0x06 (0x26) reserved ? ? ? ? ? ? ? ? 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 88 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 88 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 89 0x02 (0x22) porta ? ? ? ? ? ? porta1 porta0 88 0x01 (0x21) ddra ? ? ? ? ? ? dda1 dda0 88 0x00 (0x20) pina ? ? ? ? ? ? pina1 pina0 88 32. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits shou ld be written to zero if acce ssed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bi t-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/ o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 must be added to these addresses. the atmel avr mcu is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 208 atmel ata9999 [datasheet] 8096c?avr?01/13 33. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call k direct subroutine call pc k none 4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 209 atmel ata9999 [datasheet] 8096c?avr?01/13 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1 v 1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1 t 1 clt clear t in sreg t 0 t 1 33. instruction set summary (continued) mnemonics operands description operation flags #clocks 210 atmel ata9999 [datasheet] 8096c?avr?01/13 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, r r store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, r r out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a maths extension instructions add.l rd.i, rs.i 32-bit add rd.i rd.i + rs.i 1 1 adc.l rd.i, rs.i 32-bit add with carry rd.i rd.i + rs.i + c 1 1 33. instruction set summary (continued) mnemonics operands description operation flags #clocks 211 atmel ata9999 [datasheet] 8096c?avr?01/13 sub.l rd.i, rs.i 32-bit substract rd.i rd.i ? rs.i 1 1 sbc.l rd.i, rs.i 32-bit substract with carry rd.i rd.i ? rs.i ? c 1 1 cp.l rd.i, rs.i 32-bit substract rd.i ? rd.i 1 1 cpc.l rd.i, rs.i 32-bit substract with carry rd.i ? rd.i ? rs.i 1 1 rsub.l rd.i, rs.i 32-bit reverse substract rs.i rd.i ? rs.i 1 1 rsbc.l rd.i, rs.i 32-bit reverse substract with carry rs.i rd.i ? rs.i ? c 1 1 divinit.l rd.i (divider), type (optional) 32-bit div initialization, type selects shadow reg dividend rd.i , rd.i dividend 1 1 div.l rd.i (remainder), rs.i (divisor) 32-bit division (iterative) rd.i divider / divisor (iterative) 1 1 div.ll rd.ii (remainder), rs.ii (divisor) 64-bit division (iterative) rd.ii divider / divisor (iterative) 1 2 mov.l rd.i, rs.i 32-bit moy rd.i rd.i 1 1 mov.ll rd.ii, rs.ii 64-bit moy rd.ii rd.ii 1 2 tst.l rd.i 32-bit test for zero or neg. rd.i rd.i ? rd.i 1 1 tsl:ll rd.ii 64-bit test for zero or neg. rd.ii rd.ii ? rd.ii 1 2 lsr.l rd.i 32-bit logical shift right rd.i(n) rd.i(n+1), rd.i(31) 0, c rd.i(0) 1 1 lsr.ll rd.ii 64-bit logical shift right rd.ii(n) rd.ii(n+1), rd.ii(31) 0, c rd.ii(0) 1 2 asr.l rd.i 32-bit arithmetic shift right rd.i(n) rd.i(n+1), n = 0...30, c rd.i(0) 1 1 asr.ll rd.ii 64-bit arithmetic shift right rd.ii(n) rd.ii(n+1), n = 0...30, c rd.ii(0) 1 2 ror.l rd.i 32-bit rotate right rd.i(31) c, rd.i(n) rd.i(n+1), c rd.i(0) 1 1 ror.ll rd.ii 64-bit rotate right rd.ii(31) c, rd.ii(n) rd.ii(n+1), c rd.ii(0) 1 2 neg.l rd.i 32-bit two?s complement rd.i $0 ? rd.i 1 1 neg.ll rd.ii 64-bit two?s complement rd.ii $0 ? rd.ii 1 2 negts.l rd.i 32-bit two?s complement if t set rd.i $0 ? rd.i 1 1 negts.ll rd.ii 64-bit two?s complement if t set rd.ii $0 ? rd.ii 1 2 abs.l rd.i 32-bit absolute value t rd.i[31], rd.i abs(rd.i) 1 1 abs.ll rd.ii 64-bit absolute value t rd.ii[63], rd.ii abs(rd.ii) 1 2 absxt.l rd.i 32-bit absolute value, sign xor t t t rd.i[31], rd.i abs(rd.i) 1 1 absxt.ll rd.ii 64-bit absolute value, sign xor t t t rd.ii[63], rd.ii abs(rd.ii) 1 2 mul.w rd.w, rx.w, ry.w 16-bit multiplication with 16-bit result rd.w rx.w * ry.w (uu) 2 3 mull.w rd.i, rx.w, ry.w 16-bit multiplication with 32-bit result rd.i rx.w * ry.w (uu) 2 3 mulls.w rd.i, rx.w, ry.w 16-bit signed multiplication with 32-bit result rd.i rx.w * ry.w (ss) 2 4 mullsu.w rd.i, rx.w, ry.w 16-bit signed unsigned multiplication with 32-bit result rd.i rx.w * ry.w (su) 2 4 mul.l rd.i, rx.i, ry.i 32-bit multiplication with 32-bit result rd.i rx.i * ry.i (uu) 2 5 mull.l rdh.i, rdl.i, rx.i, ry.i 32-bit multiplication with 64-bit result rdh.i, rdl.i rx.i * ry.i (uu) 2 6 mulls.l rdh.i, rdl.i, rx.i, ry.i 32-bit signed multiplication with 64-bit result rdh.i, rdl.i rx.i * ry.i (ss) 2 6 mulsu.l rdh.i, rdl.i, rx.i, ry.i 32-bit signed unsigned multiplication with 64-bit result rdh.i, rdl.i rx.i * ry.i (su) 2 6 mul.ll rdh.i, rdl.i, rx.ii, ry.ii, rdh.i, rdl.i, != rxy.ii 64-bit multiplication with 64-bit result rdh.i, rdl.i rx.ii * ry.ii (uu) 2 12 33. instruction set summary (continued) mnemonics operands description operation flags #clocks 212 atmel ata9999 [datasheet] 8096c?avr?01/13 34. operating circuit figure 34-1. operating circuit without watchdog c 17 c 3 c 13 c 15 r 1 c 13 c 11 c 12 c 9 c 4 c 6 c 10 c 7 c 5 r 7 vcc reset/dw pb7/miso pb6/mosi pb5/sck programming debug pb4 pb3/txd pb2 pb1/rxd pb0 en rxd div/on txd nres sp_mode lin c 16 r 2 r 3 c 8 r 5 r 4 r 6 d 1 gnd gnd avcc ni pi pa1 pa0 vref c 1 vcc pv1 nv1 vbatt pvreg vreg gnd atmega32hve2/64hve2 gnd vs mode ntrig tm wd_osc vrefgnd nv2 pv2 gnd ubat lin 213 atmel ata9999 [datasheet] 8096c?avr?01/13 figure 34-2. operating circuit with watchdog c 17 c 3 c 13 c 15 r 1 c 13 c 11 c 12 c 9 c 4 c 6 c 10 c 7 c 5 r 7 vcc reset/dw pb7/miso pb6/mosi pb5/sck programming debug pb4 pb3/txd pb2 pb1/rxd pb0 en rxd div/on txd nres sp_mode lin c 16 r 2 r 3 c 8 r 5 r 4 d 1 gnd vref c 1 vcc pv1 nv1 vbatt pvreg vreg gnd atmega32hve2/64hve2 gnd vs mode ntrig tm wd_osc vrefgnd nv2 pv2 gnd ubat lin gnd avcc ni pi pa1 pa0 214 atmel ata9999 [datasheet] 8096c?avr?01/13 35. ordering information extended type number package moq atmega32hve2-plpw qfn48, 7 7 1,000 pieces atmega32hve2-plqw qfn48, 7 7 4,000 pieces atmega64hve2-plpw qfn48, 7 7 1,000 pieces atmega64hve2-plqw qfn48, 7 7 4,000 pieces 215 atmel ata9999 [datasheet] 8096c?avr?01/13 36. packaging information 36.1 markings as a minimum, the devices will be marked with the following: date code (year and week number) atmel ? part number package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5130.01-4 3 09/07/11 package: vqfn_7x7_48l exposed pad 5.6x5.6 common dimensions (unit of measure = mm) min nom note max symbol standard singulation process dimensions in mm specifications according to din technical drawings 0.02 0.05 0.0 a1 77.1 6.9 e 0.23 0.3 0.16 b 0.5 bsc e 0.4 0.5 0.3 l 5.6 5.75 5.45 e2 5.6 5.75 5.45 d2 77.1 6.9 d 0.2 0.25 0.15 a3 0.9 1 0.8 a top view d 48 1 12 pin 1 id e side view a3 a a1 b l a (10:1) bottom view e d2 48 37 13 1 12 24 25 36 e2 a 216 atmel ata9999 [datasheet] 8096c?avr?01/13 37. revision history please note that the following page numbers referred to in this se ction refer to the specific revision mentioned, not to this document. revision no. history 8096c-avr-01/13 ? section 26.5 ?diagnosis mode? on page 149 updated 8096b-avr-11/12 ? section 27.3 ?vtemp base and vtemp slope ? on page 161 updated ? section 29.8.9 ?reading the signature row from software? on page 173 updated atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo building 1-6-4 osaki shinagawa-ku, tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8096c?avr?01/13 disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? 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